Patent US5057907A successfully refreshed from Google Patents.
US5057907A
Expired / Lapsed
US
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Method and structure for forming vertical semiconductor interconnection
Assignee: National Semiconductor Corp
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Filing: 1990-06-11
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Granted: 1991-10-15
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Expires: 2010-06-11
Abstract
Abstract An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure. In one embodiment, the portion of the tape opposite the area to which the integrated circuit die is to be inner lead bonded includes secondary metallization regions. Suitable vias in the tape contact these secondary metallization regions to selected ones of the metallic leads which are to be inner lead bonded to the integrated circuit. In one embodiment of this invention, the secondary metallization areas are fabricated sufficiently large to allow the mounting of additional components, for example chip capacitors used to filter the supply voltages applied to the integrated circuit. A method for forming is also taught.
Inventors
- 👤 Boon K. Ooi
- 👤 Shiann-Ming Liou
- 👤 Ka-Heng The
- 👤 Norman L. Gould
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:21
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/688; H10W90/00; H10W90/401; H10W72/00; H10W72/01; H10W90/20; H10W90/284; H10W90/288; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
152 words
A semiconductor device package comprising: a substrate including a first surface; and a plurality of individual integrated circuit tape assemblies electrically and physically mounted on said substrate, each of said individual integrated circuit tape assemblies comprising: a first tape portion having a first surface including metallic interconnects to which is inner lead bonded an integrated circuit, said first tape portion being disposed such that said first surface is at a selected non zero angle from said first surface of said substrate; a second tape portion having a first surface including metallic interconnects which are outer lead bonded to said first surface of said substrate; and a formed portion connecting said first and second tape portions, said formed portion serving to cause said first tape portion to be disposed at said selected non zero angle from said second tape portion, said formed portion comprising metallic interconnects and being substantially devoid of said tape.
Claim 2
Dependent Claim
152 words
A semiconductor device package comprising: a substrate including a first surface; and a plurality of individual integrated circuit tape assemblies electrically and physically mounted on said substrate, each of said individual integrated circuit tape assemblies comprising: a first tape portion having a first surface including metallic interconnects to which is inner lead bonded an integrated circuit, said first tape portion being disposed such that said first surface is at a selected non zero angle from said first surface of said substrate; a second tape portion having a first surface including metallic interconnects which are outer lead bonded to said first surface of said substrate; and a formed portion connecting said first and second tape portions, said formed portion serving to cause said first tape portion to be disposed at said selected non zero angle from said second tape portion, said formed portion comprising metallic interconnects and being substantially devoid of said tape.
Claim 3
Dependent Claim
41 words
A structure as in claim 1 wherein said first tape portion includes a third tape portion which extends generally above said integrated circuit, and including a first surface having said metallic interconnects for said inner lead bonding to said integrated circuit.
Claim 4
Dependent Claim
97 words
A structure as in claim 2 wherein said third tape portion comprises: a first region having on said first surface a first plurality of locations for inner lead bonding to associated bonding locations on said integrated circuit; a second region having on said first surface a second plurality of locations for inner lead bonding to associated bonding locations on said integrated circuit; and one or more electrical interconnects extending on said third tape portion generally from said first region to said second region to provide electrical connection to said second plurality of locations for inner lead bonding.
Claim 5
Dependent Claim
91 words
An integrated circuit tape assembly comprising: a first tape portion having a first surface including metallic interconnects for inner lead bonding to an integrated circuit; a second tape portion having a first surface including metallic interconnects for outer lead bonding to a substrate; and a formed portion connecting said first and second tape portions, said formed portion serving to cause said first tape portion to be disposed at a selected non zero angle from said second tape portion, said formed portion including metallic interconnects and being substantially devoid of said tape.
Claim 6
Dependent Claim
91 words
An integrated circuit tape assembly comprising: a first tape portion having a first surface including metallic interconnects for inner lead bonding to an integrated circuit; a second tape portion having a first surface including metallic interconnects for outer lead bonding to a substrate; and a formed portion connecting said first and second tape portions, said formed portion serving to cause said first tape portion to be disposed at a selected non zero angle from said second tape portion, said formed portion including metallic interconnects and being substantially devoid of said tape.
Claim 7
Dependent Claim
46 words
A structure as in claim 4 which further comprises a third tape portion formed as part of said first tape portion and extending generally above said integrated circuit, and having a first surface including said metallic interconnects for said inner lead bonding to said integrated circuit.
Claim 8
Dependent Claim
92 words
A structure as in claim 5 wherein said third tape portion comprises: a first region having on said first surface a first plurality of locations for inner lead bonding to associated bonding locations on said integrated circuit; a second region having on said first surface a second plurality of locations for inner lead bonding to associated bonding locations on said integrated circuit; and one or more electrical interconnects extending generally from said first region to said second region to provide electrical connection to said second plurality of locations for inner lead bonding.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |