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US5057794A
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Phase-locked loop with pattern controlled bandwidth circuit
Assignee: Level One Communications Inc
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Filing: 1991-02-26
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Granted: 1991-10-15
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Expires: 2011-02-26
Abstract
Abstract An all-digital phase-locked loop (ADPLL) is disclosed having a wide bandwidth while maintaining relatively small steps for phase error correction. A random walk filter with memory and a pattern sensitive phase adjustment circuit cooperate to control the ADPLL frequency/phase adjustment rate by taking multiple, relatively smnall steps in phase error correction at fixed intervals of time. A short cycle occurs when the phase disparity is large, interrupting the execution of the fixed interval cycle expediting the ADPLL phase lock time without sacrificing resolution in the phase error correction steps.
Inventors
- 👤 Cheng C. Shih
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:26
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992; H03L7/085; H03L7/089
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
227 words
A phase-locked loop having a pattern controlled bandwidth circuit, a phase detector with an output and a digitally controlled oscillator having an input and an output, the pattern controlled bandwidth circuit comprising: a) an up/down counting random walk filter with memory having an input and an output, the input coupled to the phase detector output, the random walk filter with memory, in response to a first overflow count, producing a count up pulse on the output and presetting to a first biased count biased towards a second overflow count, and in response to a first underflow count, the random walk filter with memory producing a count down pulse on the output and presetting to a second biased count biased towards a second underflow count; and b) a pattern sensitive phase adjuster circuit having an input, an output, and first and second counter means coupled therebetween, the input coupled to the output of the random walk filter with memory, the output coupled to the digitally controlled oscillator input, the pattern sensitive phase adjuster circuit providing a series of pulses for controlling the digitally controlled oscillator frequency in response to stimulus from the random walk filter with memory, wherein first counter means provides a time interval value between pulses in the series and second counter means provides a quantity value for a number of pulses within the time interval.
Claim 2
Dependent Claim
227 words
A phase-locked loop having a pattern controlled bandwidth circuit, a phase detector with an output and a digitally controlled oscillator having an input and an output, the pattern controlled bandwidth circuit comprising: a) an up/down counting random walk filter with memory having an input and an output, the input coupled to the phase detector output, the random walk filter with memory, in response to a first overflow count, producing a count up pulse on the output and presetting to a first biased count biased towards a second overflow count, and in response to a first underflow count, the random walk filter with memory producing a count down pulse on the output and presetting to a second biased count biased towards a second underflow count; and b) a pattern sensitive phase adjuster circuit having an input, an output, and first and second counter means coupled therebetween, the input coupled to the output of the random walk filter with memory, the output coupled to the digitally controlled oscillator input, the pattern sensitive phase adjuster circuit providing a series of pulses for controlling the digitally controlled oscillator frequency in response to stimulus from the random walk filter with memory, wherein first counter means provides a time interval value between pulses in the series and second counter means provides a quantity value for a number of pulses within the time interval.
Claim 3
Dependent Claim
51 words
A phase-locked loop in accordance with claim 1, wherein the random walk filter with memory comprises a presettable N-bit up/down counter wherein the counter is preset to a value of 3N/4 in response to an overflow count and is preset to a value of N/4 in response to an underflow count.
Claim 4
Dependent Claim
52 words
A phase-locked loop in accordance with claim 2, wherein the random walk filter with memory further comprises selection means for selecting the random walk filter with memory to function as a conventional random walk filter having the counter preset on an underflow and an overflow count to a midpoint count of N/2.
Claim 5
Dependent Claim
69 words
A phase-locked loop in accordance with claim 1, wherein the pattern sensitive phase adjuster circuit comprises: 1) preset means for presetting first counting means to an initial count and presetting second counting means to a rollover count in response to stimulus from the random walk filter with memory; and 2) disabling means for disabling first and second counting means in response to first counting means reaching a terminal count.
Claim 6
Dependent Claim
38 words
A phase-locked loop in accordance with claim 4, wherein the pattern sensitive phase adjuster circuit further comprises means for short cycling first and second counting means in response to a stimulus from the random walk filter with memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |