US4712224A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Offset digitally controlled oscillator
Assignee: Boeing North American Inc
•
Filing: 1986-10-09
•
Granted: 1987-12-08
•
Expires: 2006-10-09
Abstract
Abstract An all digital equivalent to a voltage controlled oscillator with low intrinsic jitter and the absence of sample aliasing within a nonzero bandwidth, the offset (non-symmetrical) digitally controlled oscillator comprising a divider (divide by n or n-1) which is timed from a high speed reference clock, a 2 m counter and a digital comparator. The divider divides the high speed reference clock signal so that for every thirty second cycle of the high speed reference clock a pulse is output from the present invention. The output pulse is input to the 2 m counter and increments same. The 2 m counter counts the number of output cycles (or pulses) that have occurred since the last phase adjustment and comares this m-bit number to the input to the present invention. When the output of the 2 m counter becomes greater than or equal to the input, a divide by n-1 signal is sent to the divider which shortens the output cycle and adjusts the average output frequency and phase. The 2 m counter is reset to a value of zero each time a divide by n-1 occurs.
Inventors
- 👤 Blaine J. Nelson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:23
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
209 words
An offset digitally controlled oscillator for receiving an input signal representing a digital number and generating an output pulse signal having a linear transfer function, said offset digitally controlled oscillator comprising: divider means operatively coupled to receive a reference clock signal of a predetermined frequency and structured to divide said reference clock signal by n and provide an output pulse signal for evewry n cycle of the reference clock signal; counter means operatively coupled to receive said output pulse signal from said divider means and to provide an output signal representing the count in said counter means, said counter means structured to be incremented by said output pulse signal received from said divider means; digital comparator means operatively coupled to receive the output signal from said counter means and operatively coupled to receive said input signal representing a digital number, said digital comparator means operatively coupled to provide an output signal to said divider means when said output signal from said counter means is at least equal to or greater than said input signal representing a digital number; and said divider means being structured, when receiving said output signal from said digital comparator, to divide the reference clock signal by n-1 and to reset the counter means to zero.
Claim 2
Dependent Claim
209 words
An offset digitally controlled oscillator for receiving an input signal representing a digital number and generating an output pulse signal having a linear transfer function, said offset digitally controlled oscillator comprising: divider means operatively coupled to receive a reference clock signal of a predetermined frequency and structured to divide said reference clock signal by n and provide an output pulse signal for evewry n cycle of the reference clock signal; counter means operatively coupled to receive said output pulse signal from said divider means and to provide an output signal representing the count in said counter means, said counter means structured to be incremented by said output pulse signal received from said divider means; digital comparator means operatively coupled to receive the output signal from said counter means and operatively coupled to receive said input signal representing a digital number, said digital comparator means operatively coupled to provide an output signal to said divider means when said output signal from said counter means is at least equal to or greater than said input signal representing a digital number; and said divider means being structured, when receiving said output signal from said digital comparator, to divide the reference clock signal by n-1 and to reset the counter means to zero.
Claim 3
Dependent Claim
18 words
An offset digitally controlled oscillator according to claim 1 wherein the counter means comprises a 2 m counter.
Claim 4
Dependent Claim
13 words
An offset digitally controlled oscillator according to claim 2 wherein m equals 8.
Claim 5
Dependent Claim
13 words
An offset digitally controlled oscillator according to claim 1 wherein n equals 32.
Claim 6
Dependent Claim
22 words
An offset digitally controlled oscillator according to claim 1 wherein the predetermined frequency of the reference clock signal substantially equals 49 MHz.
Claim 7
Independent Claim
151 words
A method of providing an output clock signal having a linear transfer function upon receipt of an input signal representing a digital number, said method comprising the steps of: (a) providing a reference clock signal of a predetermined frequency; (b) dividing said reference clock signal by n to provide said output clock signal for every n th cycle of the reference clock signal; (c) counting each output clock signal and providing an incremented total count of the output clock signals; (d) comparing the incremented total count of the output clock signals with the input signal representing a digital number; (e) dividing said reference clock signal by n-1 to provide said output clock signal for every n th -1 cycle of the reference clock signal when said incremented total count of the output clock signal equals or exceeds the input signal representing a digital number; and (f) repeating steps (a) through (f).
Claim 8
Independent Claim
151 words
A method of providing an output clock signal having a linear transfer function upon receipt of an input signal representing a digital number, said method comprising the steps of: (a) providing a reference clock signal of a predetermined frequency; (b) dividing said reference clock signal by n to provide said output clock signal for every n th cycle of the reference clock signal; (c) counting each output clock signal and providing an incremented total count of the output clock signals; (d) comparing the incremented total count of the output clock signals with the input signal representing a digital number; (e) dividing said reference clock signal by n-1 to provide said output clock signal for every n th -1 cycle of the reference clock signal when said incremented total count of the output clock signal equals or exceeds the input signal representing a digital number; and (f) repeating steps (a) through (f).
Claim 9
Dependent Claim
10 words
The method according to claim 6 wherein n equals 32.
Claim 10
Dependent Claim
15 words
The method according to claim 6 wherein said reference clock signal substantially equals 49 MHz.
References Cited (Backward Citations)
US3662330A
Cited
US3959737A
Cited
US4184068A
Cited
US4423381A
Cited
US4468797A
Cited
GB2095444A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-07 | 1991-06-08 | 1991-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-07 | 1995-06-08 | 1995-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-07 | 1999-06-08 | 1999-12-08 | $7700.00 | Window Closed / Lapsed |