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Patent US5057792A successfully refreshed from Google Patents.
US5057792A
Expired / Lapsed
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Current mirror
Assignee: Motorola Solutions Inc
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Filing: 1990-07-23
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Granted: 1991-10-15
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Expires: 2010-07-23
Abstract
Abstract The invention relates to a current mirror circuit (28) comprising: an input node (29); a first simple current mirror (30) of a first type, such as pnp bipolar technology, having an input coupled to said input node (29) and an output; a second simple current mirror (32) of a second semiconductor type, such as npn bipolar technology, having an input coupled to said output of said first simple current mirror and an output; a third simple current mirror (34) of said first semiconductor type having an input coupled to said output of said second simple current mirror and an output coupled to said input node (29); and an output node (31) coupled to said second simple current mirror (32) so as to receive the sum of the input and output currents of said second simple current mirror flowing in a common terminal thereof.
Inventors
- 👤 Michael J. Gay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:40
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265; H; H03; H03F; H03F3/00; H03F3/34; H03F3/343
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
121 words
A current mirror circuit comprising: an input node; a first simple current mirror of a first semiconductor type having an input coupled to said input node and an output; a second simple current mirror of a second semiconductor type having an input coupled to said output of said first simple current mirror and an output; a third simple current mirror of said first semiconductor type having an input coupled to said output of said second simple current mirror and an output coupled to said input node; and an output node coupled to said second simple current mirror so as to receive the sum of the input and output currents of said second simple current mirror flowing in a common terminal thereof.
Claim 2
Dependent Claim
121 words
A current mirror circuit comprising: an input node; a first simple current mirror of a first semiconductor type having an input coupled to said input node and an output; a second simple current mirror of a second semiconductor type having an input coupled to said output of said first simple current mirror and an output; a third simple current mirror of said first semiconductor type having an input coupled to said output of said second simple current mirror and an output coupled to said input node; and an output node coupled to said second simple current mirror so as to receive the sum of the input and output currents of said second simple current mirror flowing in a common terminal thereof.
Claim 3
Dependent Claim
93 words
A current mirror circuit according to claim 1 wherein said second simple current mirror comprises first and second transistors having a common base electrode, the collector electrode of said first transistor is coupled to said common base electrode and forms the input of said second simple current mirror, the collector electrode of said second transistor forms the output of said second simple current mirror, and the emitter electrodes of said first and second transistors are coupled together to said common terminal which is coupled to said output node of said current mirror circuit.
Claim 4
Dependent Claim
83 words
A current mirror circuit according to claim 1 wherein said first simple current mirror comprises first and second transistors having a common base electrode, the collector electrode of said first transistor is coupled to said common base electrode and forms the input of said first simple current mirror, the collector electrode of said second transistor forms the output of said first simple current mirror, and the emitter electrodes of said first and second transistors are coupled together to a first reference potential line.
Claim 5
Dependent Claim
83 words
A current mirror circuit according to claim 1 wherein said third simple current mirror comprises first and second transistors having a common base electrode, the collector electrode of said first transistor is coupled to said common base electrode and forms the input of said third simple current mirror, the collector electrode of said second transistor forms the output of said third simple current mirror, and the emitter electrodes of said first and second transistors are coupled together to a first reference potential line.
Claim 6
Dependent Claim
26 words
A current mirror circuit according to claim 1 wherein said first semiconductor type comprises npn bipolar technology and said second semiconductor type comprises pnp bipolar technology.
Claim 7
Dependent Claim
26 words
A current mirror circuit according to claim 1 wherein said first semiconductor type comprises pnp bipolar technology and said second semiconductor type comprises npn bipolar technology.
References Cited (Backward Citations)
US4339729A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |