Clock formation circuit with phase locked loop control

Claim 2

A clock formation circuit for forming from a digital data signal a formation clock signal corresponding to data clocks controlling an inversion timing of said digital data signal comprising: phase difference information output means to compare a phase of said digital data single with that of said formation clock signal to provide a phase difference information signal having a saw-tooth periodical waveform when a frequency of said data clocks is different from that of said formation clock signal, said phase difference information signal having a level varying in accordance with a phase difference between said digital data signal and said formation clock signal; means to provide a first envelope signal having a level increasing in accordance with said phase difference information signal and decreasing at a predetermined characteristic when said phase difference information signal rapidly decreases and a second envelope signal having a level decreasing in accordance with said phase difference information signal and increasing at a predetermined characteristic when said phase difference information signal rapidly increases; means having an addition function and an integration function to provide a correction error information signal including at least an information identical to an operation information obtained by adding and then integrating said first and second envelope signals; and means to provide said formation clock signal having a frequency controlled on said correction error information signal.

Claim 3

A clock formation circuit as set forth in claim 1, and wherein said means to provide a correction error information signal comprises an inversion type amplifier having an inversion input terminal to which said first and second envelope signals are applied through resistors, respectively, and at least either of a capacitor and a series connection of a capacitor and a resistor connected between said inversion input terminal and an output terminal thereof.

Claim 4

A clock formation circuit for forming from a digital data signal a formation clock signal corresponding to data clocks controlling an inversion timing of said digital data signal comprising: phase difference information output means to compare a phase of said digital data signal with that of said formation clock signal to provide a phase difference information signal having a saw-tooth periodical waveform when a frequency of said data clocks is different from that of said formation clock signal, said phase difference information signal having a level varying in accordance with a phase difference between said digital data signal and said formation clock signal; envelope signal output means to provide a first envelope signal having a level increasing in accordance with said phase difference information signal and decreasing at a predetermined characteristic when said phase difference information signal rapidly decreases and a second envelope signal having a level decreasing in accordance with said phase difference information signal and increasing at a predetermined characteristic when said phase difference information signal rapidly increases; correction error information signal formation means having an addition function and an integration function to provide a correction error information signal including both an addition information of said first and second envelope signals and an integral information obtained by integrating said addition information; and formation clock signal output means to provide said formation clock signal having a frequency controlled on said correction error information signal.

Claim 5

A clock formation circuit for forming from a digital data signal a formation clock signal corresponding to data clocks controlling an inversion timing of said digital data signal comprising: phase difference information output means to compare a phase of said digital data signal with that of said formation clock signal to provide a phase difference information signal having a saw-tooth periodical waveform when a frequency of said data clocks is different from that of said formation clock signal, said phase difference information signal having a level varying in accordance with a phase difference between said digital data signal and said formation clock signal; envelope signal output means to provide a first envelope signal having a level increasing in accordance with said phase difference information signal and decreasing at a predetermined characteristic when said phase difference information signal rapidly decreases and a second envelope signal having a level decreasing in accordance with said phase difference information signal and increasing at a predetermined characteristic when said phase difference information signal rapidly increases; correction error information signal formation means having an addition function and an integration function to provide a correction error information signal including both an addition information of said first and second envelope signals and an integral information obtained by integrating said addition information; and formation clock signal output means to provide said formation clock signal having a frequency controlled on said correction error information signal.

Claim 6

A clock formation circuit as set forth in claim 3, and wherein said envelope signal output means comprises a pair of transistors connected in series to each other so that said transistors have emitter connected through respective capacitors connected to each other and bases to which said phase difference information signal is applied and having output terminals provided at connections of said emitters and said capacitors to provide said first and second envelope signals, respectively.

Claim 7

A clock formation circuit as set forth in claim 4, and wherein said formation clock signal output means comprises voltage control oscillator including a variable capacitor diode across which are applied said correction error information signal and a reference voltage.

Claim 8

A clock formation circuit for forming from a digital data signal a formation clock signal corresponding to data clocks controlling an inversion timing of said digital data signal comprising: phase difference information output means to compare a phase of said digital data signal with that of said formation clock signal to provide a phase difference information signal having a saw-tooth periodical waveform when a frequency of said data clocks is different from that of said formation clock signal, said phase difference information signal having a level varying in accordance with a phase difference between said digital data signal and said formation clock signal; envelope signal output means to provide a first envelope signal having a level increasing in accordance with said phase difference information signal and decreasing at a predetermined characteristic when said phase difference information signal rapidly decreases and a second envelope signal having a level decreasing in accordance with said phase difference information signal and increasing at a predetermined characteristic when said phase difference information signal rapidly increases; integration means having an addition function and an integration function to provide an additive and integral information signal identical to a signal obtained by adding and then integrating said first and second envelope signals; and formation clock signal output means to provide said formation clock signal having a frequency controlled on at least said additive and integral information signal.

Claim 9

A clock formation circuit for forming from a digital data signal a formation clock signal corresponding to data clocks controlling an inversion timing of said digital data signal comprising: phase difference information output means to compare a phase of said digital data signal with that of said formation clock signal to provide a phase difference information signal having a saw-tooth periodical waveform when a frequency of said data clocks is different from that of said formation clock signal, said phase difference information signal having a level varying in accordance with a phase difference between said digital data signal and said formation clock signal; envelope signal output means to provide a first envelope signal having a level increasing in accordance with said phase difference information signal and decreasing at a predetermined characteristic when said phase difference information signal rapidly decreases and a second envelope signal having a level decreasing in accordance with said phase difference information signal and increasing at a predetermined characteristic when said phase difference information signal rapidly increases; integration means having an addition function and an integration function to provide an additive and integral information signal identical to a signal obtained by adding and then integrating said first and second envelope signals; and formation clock signal output means to provide said formation clock signal having a frequency controlled on at least said additive and integral information signal.

Claim 10

A clock formation circuit as set forth in claim 6, and wherein said envelope signal output means comprises a pair of transistors connected in series to each other so that said transistors have emitter connected through respective capacitors connected to each other and bases to which said phase difference information signal is applied and having output terminals provided at connections of said emitters and said capacitors to provide said first and second envelope signals, respectively.

Claim 11

A clock formation circuit as set forth in claim 7, and wherein said formation clock signal output means comprises voltage control oscillator including a variable capacitor diode across which are applied an addition signal of said first and second envelope signals and said additive and integral signal thereof.