US4443769A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency search system for a phase locked loop
Assignee: RCA Corp
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Filing: 1981-09-21
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Granted: 1984-04-17
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Expires: 2001-09-21
Abstract
Abstract A sampling PLL circuit features a frequency sweep caused by an offset voltage applied to an integrator to avoid false lock ups. At one end of the frequency range the polarity of the offset signal can be reversed. The error voltage can be sampled during a television vertical or horizontal blanking period. Once proper lock up is achieved, the offset signal can be removed.
Inventors
- 👤 Felix Aschwanden
- 👤 Willem H. Groeneweg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:02
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/12
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
147 words
An apparatus for locking a phase locked loop onto a modulated reference signal, said apparatus comprising deriving means for deriving from said reference signal a demodulated signal and an error signal; sampling means for sampling said error signal, avoiding means for avoiding lock ups of said loop on other than said reference signal, integrating means for integrating the sampled signal, said avoiding means comprising applying means for applying an offset signal to said integrating means, said applying means comprising ceasing means for ceasing to apply said offset signal once locking is achieved, said ceasing means comprising an automatic gain control processor coupled to said deriving means to receive said demodulated signal, a comparator having a pair of inputs respectively coupled to said processor and to a comparator reference signal source, and a switch controlled by said comparator and coupled between said applying means and said integrating means.
Claim 2
Independent Claim
147 words
An apparatus for locking a phase locked loop onto a modulated reference signal, said apparatus comprising deriving means for deriving from said reference signal a demodulated signal and an error signal; sampling means for sampling said error signal, avoiding means for avoiding lock ups of said loop on other than said reference signal, integrating means for integrating the sampled signal, said avoiding means comprising applying means for applying an offset signal to said integrating means, said applying means comprising ceasing means for ceasing to apply said offset signal once locking is achieved, said ceasing means comprising an automatic gain control processor coupled to said deriving means to receive said demodulated signal, a comparator having a pair of inputs respectively coupled to said processor and to a comparator reference signal source, and a switch controlled by said comparator and coupled between said applying means and said integrating means.
Claim 3
Dependent Claim
21 words
An apparatus as claimed in claim 1, wherein said integrating means has a relatively large time constant for high noise immunity.
Claim 4
Dependent Claim
32 words
An apparatus as claimed in claim 1, wherein said applying means comprises reversing means for reversing the polarity of said offset signal when a selected amplitude of the integrated signal is achieved.
Claim 5
Dependent Claim
15 words
An apparatus as claimed in claim 3, wherein said reversing means comprises a Schmitt trigger.
Claim 6
Dependent Claim
185 words
Apparatus for phase-lock-loop demodulating a double side-band suppressed-carrier signal modulated by a video signal, said apparatus comprising: means for producing an error signal from said suppressed-carrier signal including a voltage controlled oscillator, a phase shifter coupled to said oscillator for establishing first and second reference carriers in quadrature phase relationship, first and second balanced demodulators coupled respectively to said first and second reference carriers and each coupled to said suppressed-carrier signal for respectively providing a demodulated video signal and said error signal; means for sampling said error signal during the horizontal and vertical blanking intervals of said video signal; means for integrating the sampled error signal; means, coupled to said integrating means, for avoiding lock ups on other than said suppressed-carrier signal; and means for disabling said avoiding means upon achieving correct lock up; said disabling means comprising means for deriving an automatic gain control signal from said demodulated video signal, a comparator having a pair of inputs coupled to respectively receive said automatic gain control signal, and a selected reference signal, and a gate coupled to said comparator for control of said avoiding means.
Claim 7
Dependent Claim
185 words
Apparatus for phase-lock-loop demodulating a double side-band suppressed-carrier signal modulated by a video signal, said apparatus comprising: means for producing an error signal from said suppressed-carrier signal including a voltage controlled oscillator, a phase shifter coupled to said oscillator for establishing first and second reference carriers in quadrature phase relationship, first and second balanced demodulators coupled respectively to said first and second reference carriers and each coupled to said suppressed-carrier signal for respectively providing a demodulated video signal and said error signal; means for sampling said error signal during the horizontal and vertical blanking intervals of said video signal; means for integrating the sampled error signal; means, coupled to said integrating means, for avoiding lock ups on other than said suppressed-carrier signal; and means for disabling said avoiding means upon achieving correct lock up; said disabling means comprising means for deriving an automatic gain control signal from said demodulated video signal, a comparator having a pair of inputs coupled to respectively receive said automatic gain control signal, and a selected reference signal, and a gate coupled to said comparator for control of said avoiding means.
Claim 8
Dependent Claim
21 words
Apparatus as claimed in claim 5, wherein said means for avoiding comprises a Schmitt trigger having a pair of threshold levels.
References Cited (Backward Citations)
GB641900A
Cited
GB655553A
Cited
GB1272447A
Cited
US3775695A
Cited
GB1509913A
Cited
US4117420A
Cited
US4146843A
Cited
US4115745A
Cited
GB2008347A
Cited
WO1979000905A1
Cited
US4222074A
Cited
GB2043373A
Cited
GB2050731A
Cited
US4291336A
Cited
GB2077533A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-04-17 | 1987-10-17 | 1988-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-04-17 | 1991-10-17 | 1992-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-04-17 | 1995-10-17 | 1996-04-17 | $7700.00 | Window Closed / Lapsed |