Cache memory for use with multiprocessor systems

Claim 1

A multiprocessor system including a plurality of cache memories, wherein each cache memory is dedicated to a single processor and wherein a common main memory is shared by a plurality of processors via a system bus and wherein each cache memory includes a data storage section for saving data for quick reference by the processor allocated to the cache memory, the cache memory comprises: first means for saving tag addresses each corresponding to one data stored in said data storage section, said first means being configured to have first and second ports so as to be independently accessible by the processor via said first port and by another cache memory via said second port; second means for saving tag address valid information data each of which indicates whether or not the corresponding tag address is valid, said second means being configured to have third and fourth ports so as to be independently accessible by the processor via said third port and by another cache memory via said fourth port; third means coupled to said first means via said first port and to said second means via said third port and to the processor, said third means comparing a tag address applied from said first means with a tag address from the processor and checking to see if the tag address applied from the processor is identical with the tag address from said first means and valid and outputting a first hit signal in the event that the tag address applied from the processor is identical with the tag address from said first means and valid; fourth means arranged between said system bus and both of said first and second means, said fourth means being coupled to said first means via said second port and to said second means via said fourth port, said fourth means, in the event of a cache update in another cache memory, allowing said another cache memory to access said first and second means via said second and fourth ports, respectively; fifth means coupled to said first means via said second port and to said second means via said fourth port and to said fourth means, said fifth means comparing a tag address applied from said first means with a tag address applied from said another cache memory via said fourth means in the event of a cache update in another cache memory, said fifth means checking to see if the tag address applied via said fourth means is identical with the tag address from said first means and valid and outputting a second hit signal in the event that the tag address applied via said fourth means is identical with the tag address from said first means and valid; and six means, arranged between said fifth means and said fourth port of said second means, invalidates the tag address valid information data within said second means in response to said second hit signal.