Apparatus and method for data copy consistency in a multi-cache data processing unit

Claim 1

A cache memory unit for use in a data processing system, said data processing system including a plurality of data processing units coupled to a system bus, each data processing unit having a cache memory unit with a write back or write thru mode of operation whereby the result of every associated data processing unit operation is stored into the cache memory unit associated therewith, comprising: a plurality of addressable storage locations for storing signal groups identified by and associated with an address signal group; a status register means associated with each of said locations for storing status signals identifying parameters of a signal group stored in said associated locations; activity means for applying an associated address signal group to said system bus for each signal group in said main memory unit retrieved by said associated data processing unit, said activity means for applying a first first control signal and an associated address signal group to said system bus for each signal group altered by said associated data processing unit, said activity means for applying a second control signal to said system bus when data processing unit not associated with said cache memory unit retrieves a signal group from said main memory unit also stored in said cache memory unit; and update means coupled to said system bus and responsive to address signal groups to said control signals applied to said system bus for changing status signal in said status register associated for signal groups stored in said cache memory unit.