Video memory control apparatus

Claim 2

A video memory control apparatus comprising: a plurality of memories; a selection circuit for selectively outputting respective outputs of said plurality of memories; a clock pulse generation circuit for generating a clock pulse signal to be supplied to said plurality of memories for performing at least one of writing a video signal into said plurality of memories and reading said video signal from said plurality of memories; supply means for supplying said plurality of memories with said clock pulse signal generated by said clock pulse generation circuit to thereby perform at least one of said writing and reading of said video signal; selection means for controlling said selection circuit based on a signal relating to a vertical synchronizing signal of said video signal to thereby select one of said plurality of memories so as to derive a video signal output of said selected one memory as an output of said selection circuit; and stop means for stopping supply of said clock pulse signal to said plurality of memories except for said one memory selected by said selection means.

Claim 3

A video memory control apparatus according to claim 1, wherein said plurality of memories are respectively constituted by integrated circuits; said selection circuit includes a plurality of input terminals correspondingly connected to respective outputs of said plurality of integrated circuits, an output terminal, and a selector member; said selection means acts to control said selector member based on a vertical synchronizing signal of said video signal so as to cause said selector member to select one of said plurality of input terminals; and said stop means acts to stop supply of a clock pulse signal which is to be supplied, for dealing with said video signal, to said plurality of input terminals except for said selected one input terminal and then to at least one of said plurality of memories.

Claim 4

A video memory control apparatus according to claim 1, wherein said plurality of memories includes two C-MOS integrated circuits.

Claim 5

A video memory control apparatus comprising: a plurality of memories; a selection circuit for selectively outputting respective outputs of said plurality of memories; a clock pulse generation circuit for generating a clock pulse signal to be supplied to said plurality of memories for performing at least one of writing a video signal into said plurality of memories and reading said video signal from said plurality of memories; supply means for supplying said plurality of memories with said clock pulse signal generated by said clock pulse generation circuit to thereby perform at least one of said writing and reading of said video signal; first control means for controlling said selection circuit based on a signal relating to a vertical synchronizing signal or said video signal to thereby select one of said plurality of memories so as to derive a video output of said selected one memory as an output of said selection circuit; and second control means which allows said clock pulse to be supplied to said one memory selected by said first control means but does not allow said clock pulse signal to be supplied to said plurality of memories other than said selected one memory.

Claim 6

A video memory control apparatus comprising: a plurality of memories; a selection circuit for selectively outputting respective outputs of said plurality of memories; a clock pulse generation circuit for generating a clock pulse signal to be supplied to said plurality of memories for performing at least one of writing a video signal into said plurality of memories and reading said video signal from said plurality of memories; supply means for supplying said plurality of memories with said clock pulse signal generated by said clock pulse generation circuit to thereby perform at least one of said writing and reading of said video signal; first control means for controlling said selection circuit based on a signal relating to a vertical synchronizing signal or said video signal to thereby select one of said plurality of memories so as to derive a video output of said selected one memory as an output of said selection circuit; and second control means which allows said clock pulse to be supplied to said one memory selected by said first control means but does not allow said clock pulse signal to be supplied to said plurality of memories other than said selected one memory.

Claim 7

A video memory control apparatus according to claim 4, wherein said plurality of memories are respectively constituted by integrated circuits; said selection circuit includes a plurality of input terminals correspondingly connected to respective outputs of said plurality of integrated circuits, an output terminal, and a selector member; said first control means acts to control said selector member based on a vertical synchronizing signal of said video signal so as to cause said selector member to select one of said plurality of input terminals; and said second control means allows said clock pulse signal to be supplied to said one selected input terminal and does not allow said clock pulse signal to be supplied to said plurality of input terminals except for said selected one input terminal.

Claim 8

A video memory control apparatus according to claim 5, wherein said plurality of memories include two C-MOS integrated circuits.