US5055908A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor circuit having metallization with TiW
Assignee: Texas Instruments Inc
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Filing: 1987-07-27
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Granted: 1991-10-08
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Expires: 2007-07-27
Abstract
Abstract The disclosure relates to a semiconductor circuit on a single chip, preferably of gallium arsenide, wherein insulating layers with vias therein for receiving metallization include a thin silicon nitride layer beneath a relatively much thicker silicon oxide layer with the nitride exposed on the via side walls to contact gold in the metallization within the via. The disclosure further includes metallization formed as a TiW/Au/TiW sandwich wherein the TiW layer contacting the insulator on the substrate is formed of a first tensile film of TiW with a compressive film of TiW of substantially the same thickness thereover and in contact therewith to lower the tensile force applied by the tensile layer, yet maintain the resultant force tensile.
Inventors
- 👤 Clyde R. Fuller
- 👤 Joseph B. Delaney
- 👤 Robbie W. Skinner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W20/41; H10W20/425; H10W20/44; H10W20/4403; H10W20/4432
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
71 words
A semiconductor circuit which comprises: (a) a semiconductor substrate; and (b) metallization over said substrate, said metallization comprising: (c) a first layer of tensile stressed TiW secured to said substrate; (d) a second layer of compressive stressed TiW disposed over and in contact with said first layer; and (e) a layer of metal taken from the group consisting of gold and aluminum contacting said second film layer of compressive stressed TiW.
Claim 2
Dependent Claim
71 words
A semiconductor circuit which comprises: (a) a semiconductor substrate; and (b) metallization over said substrate, said metallization comprising: (c) a first layer of tensile stressed TiW secured to said substrate; (d) a second layer of compressive stressed TiW disposed over and in contact with said first layer; and (e) a layer of metal taken from the group consisting of gold and aluminum contacting said second film layer of compressive stressed TiW.
Claim 3
Dependent Claim
14 words
A semiconductor circuit as set forth in claim 1 wherein said metal is gold.
Claim 4
Dependent Claim
48 words
A semiconductor circuit as set forth in claim 1 wherein the tensile stress of said first layer is about 1.1×10 10 dynes/centimeter square and the compressive stress of said second layer is about 1.0×10 10 dynes/centimeter square, producing a net tensile stress of about 1×10 9 dynes/centimeter square.
Claim 5
Dependent Claim
48 words
A semiconductor circuit as set forth in claim 2 wherein the tensile stress of said first layer is about 1.1×10 10 dynes/centimeter square and the compressive stress of said second layer is about 1.0×10 10 dynes/centimeter square, producing a net tensile stress of about 1×10 9 dynes/centimeter square.
Claim 6
Dependent Claim
35 words
A semiconductor circuit as set forth in claim 1, further including a via containing insulating layer on said substrate, said metallization extending over said insulating layer and into said via, said via having side walls.
Claim 7
Dependent Claim
35 words
A semiconductor circuit as set forth in claim 2, further including a via containing insulating layer on said substrate, said metallization extending over said insulating layer and into said via, said via having side walls.
Claim 8
Dependent Claim
35 words
A semiconductor circuit as set forth in claim 3, further including a via containing insulating layer on said substrate, said metallization extending over said insulating layer and into said via, said via having side walls.
Claim 9
Dependent Claim
35 words
A semiconductor circuit as set forth in claim 4, further including a via containing insulating layer on said substrate, said metallization extending over said insulating layer and into said via, said via having side walls.
Claim 10
Dependent Claim
65 words
A semiconductor circuit as set forth in claim 5 wherein said insulating layer comprises a first layer of silicon nitride over said substrate; a second layer of silicon oxide over and contiguous with said nitride and remote from said substrate; and said via formed through said first and second layers having a portion of said first layer exposed on the side wall of said via.
Claim 11
Dependent Claim
65 words
A semiconductor circuit as set forth in claim 6 wherein said insulating layer comprises a first layer of silicon nitride over said substrate; a second layer of silicon oxide over and contiguous with said nitride and remote from said substrate; and said via formed through said first and second layers having a portion of said first layer exposed on the side wall of said via.
Claim 12
Dependent Claim
65 words
A semiconductor circuit as set forth in claim 7 wherein said insulating layer comprises a first layer of silicon nitride over said substrate; a second layer of silicon oxide over and contiguous with said nitride and remote from said substrate; and said via formed through said first and second layers having a portion of said first layer exposed on the side wall of said via.
Claim 13
Dependent Claim
65 words
A semiconductor circuit as set forth in claim 8 wherein said insulating layer comprises a first layer of silicon nitride over said substrate; a second layer of silicon oxide over and contiguous with said nitride and remote from said substrate; and said via formed through said first and second layers having a portion of said first layer exposed on the side wall of said via.
Claim 14
Dependent Claim
57 words
A semiconductor circuit which comprises: (a) a semiconductor substrate; and (b) metallization over said substrate, said metallization comprising: (c) a layer of compressive stressed TiW disposed over and coupled to said substrate; and (d) a layer of metal taken from the group consisting of gold and aluminum disposed over and contacting said layer of compressive stressed TiW.
Claim 15
Dependent Claim
57 words
A semiconductor circuit which comprises: (a) a semiconductor substrate; and (b) metallization over said substrate, said metallization comprising: (c) a layer of compressive stressed TiW disposed over and coupled to said substrate; and (d) a layer of metal taken from the group consisting of gold and aluminum disposed over and contacting said layer of compressive stressed TiW.
Claim 16
Dependent Claim
16 words
A semiconductor circuit as set forth in claim 13 wherein said layer of metal is gold.
Claim 17
Dependent Claim
28 words
A semiconductor circuit as set forth in claim 1 wherein said substrate includes a layer of silicon oxide on the surface thereof in contact with said first layer.
Claim 18
Dependent Claim
28 words
A semiconductor circuit as set forth in claim 2 wherein said substrate includes a layer of silicon oxide on the surface thereof in contact with said first layer.
Claim 19
Dependent Claim
28 words
A semiconductor circuit as set forth in claim 3 wherein said substrate includes a layer of silicon oxide on the surface thereof in contact with said first layer.
Claim 20
Dependent Claim
28 words
A semiconductor circuit as set forth in claim 4 wherein said substrate includes a layer of silicon oxide on the surface thereof in contact with said first layer.
Claim 21
Dependent Claim
28 words
A semiconductor circuit as set forth in claim 13 wherein said substrate includes a layer of silicon oxide on the surface thereof in contact with said first layer.
Claim 22
Dependent Claim
28 words
A semiconductor circuit as set forth in claim 14 wherein said substrate includes a layer of silicon oxide on the surface thereof in contact with said first layer.
References Cited (Backward Citations)
US4205227A
Cited
US4131902A
Cited
US4149307A
Cited
US4282647A
Cited
US4253881A
Cited
US4213840A
Cited
US4330343A
Cited
US4417387A
Cited
US4720908A
Cited
US4692786A
Cited
US4752813A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |