Patent US5055845A successfully refreshed from Google Patents.
US5055845A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal digitizing method and system utilizing time delay of the input signal
Assignee: Datajet Inc
•
Filing: 1989-09-13
•
Granted: 1991-10-08
•
Expires: 2009-09-13
Abstract
Abstract A circuit and method for representing in digital form information about the time and amplitude characteristic of a time-varying input signal. The time-varying input signal is delayed and the magnitudes of the time-varying input signal and its delayed version are compared to produce a digital signal representing the time characteristic of the input signal in the form of a transition in a digital output signal each time the magnitudes of the compared signals have a predetermined relationship. The predetermined relationship may be a condition of approximate equality or when the magnitude of the larger of the compared signals becomes less than the magnitude of the smaller of the compared signals. The invention also includes a circuit for outputting a digital representation of the amplitude of the time-varying input signal for each transition of said digital output signal. The circuits thus provide separate digital representations of the time and amplitude of each peak and valley of an analog or other time-varying input signal.
Inventors
- 👤 Frank Ridkosil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:43
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1532; H03M; H03M1/00; H03M1/12; H03M1/124; H03M1/1245; H03M1/1265; H03M1/127; H03M1/1275; H04; H04K; H04K1/00; H04L; H04L27/00; H04L27/02; H04L27/06; H04L7/00; H04L7/02; H04L7/027
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
118 words
A converter circuit for converting into binary information an input analog signal having a time-varying amplitude producing amplitude peaks and valleys, the converter circuit comprising digitizer means having an input for receiving the input analog signal and an output for providing a binary signal in the form of a sequence of binary states having durations responsive to the time between peaks and valleys of the input analog signal, the digitizer means including means for producing a delayed version of the input analog signal, and means for comparing the input analog signal with the delayed version and changing the state of said binary signal in response to a predetermined relationship between said input analog signal and said delayed version.
Claim 2
Dependent Claim
118 words
A converter circuit for converting into binary information an input analog signal having a time-varying amplitude producing amplitude peaks and valleys, the converter circuit comprising digitizer means having an input for receiving the input analog signal and an output for providing a binary signal in the form of a sequence of binary states having durations responsive to the time between peaks and valleys of the input analog signal, the digitizer means including means for producing a delayed version of the input analog signal, and means for comparing the input analog signal with the delayed version and changing the state of said binary signal in response to a predetermined relationship between said input analog signal and said delayed version.
Claim 3
Dependent Claim
40 words
The converter circuit of claim 1 wherein there is further provided amplifier means in said digitizer means, said amplifier means having inverting and noninverting inputs, said input receiving the input analog signal being said inverting input, and an amplifier output.
Claim 4
Dependent Claim
17 words
The converter circuit of claim 2 including feedback means coupling said amplifier output to said noninverting input.
Claim 5
Dependent Claim
60 words
The converter circuit of claim 3 wherein said feedback means comprises: first resistor means coupled across said inverting and noninverting inputs; and second resistor means coupled across said inverting and noninverting inputs; and capacitor means coupled across said noninverting input and a reference potential, wherein said capacitor means and said first and second resistor means establish a predetermined time constant.
Claim 6
Dependent Claim
43 words
The converter circuit of claim 1 wherein there is further provided preamplifier means having an input for receiving the input analog signal and an output coupled to said input of said digitizer means for providing an amplified version of the input analog signal.
Claim 7
Dependent Claim
25 words
The converter circuit of claim 5 wherein there is further provided frequency-responsive negative feedback means for coupling said input said output of said preamplifier means.
Claim 8
Dependent Claim
68 words
A circuit for representing in digital form durations between amplitude peaks and valleys of an analog time-varying input signal, the circuit comprising: means for delaying the time-varying input signal; and means for comparing the magnitudes of the time-varying input signal and the delayed time-varying input signal to produce a transition in a digital output signal each time a differential magnitude of the compared signals has a predetermined value.
Claim 9
Dependent Claim
68 words
A circuit for representing in digital form durations between amplitude peaks and valleys of an analog time-varying input signal, the circuit comprising: means for delaying the time-varying input signal; and means for comparing the magnitudes of the time-varying input signal and the delayed time-varying input signal to produce a transition in a digital output signal each time a differential magnitude of the compared signals has a predetermined value.
Claim 10
Dependent Claim
26 words
The circuit of claim 7 wherein said transition in the digital output signal is produced each time the magnitudes of the compared signals are approximately equal.
Claim 11
Dependent Claim
26 words
The circuit of claim 7 wherein said transition in the digital output signal is produced each time a reversal in magnitude of the compared signals occurs.
Claim 12
Dependent Claim
36 words
The circuit of claim 7 wherein said delaying means comprises means for delaying the time-varying input signal by an amount less than the time of one-half of the shortest expected cycle of the time-varying input signal.
Claim 13
Dependent Claim
28 words
The circuit of claim 7 including means for providing a digital representation of the amplitude of the time-varying input signal for each transition of said digital output signal.
Claim 14
Independent Claim
66 words
A method for representing in digital forms durations between amplitude peaks and valleys of an analog time-varying input signal, the method comprising the steps of: delaying the time-varying input signal; comparing the magnitudes of the time-varying input signal and the delayed time-varying input signal; and producing a transition in a digital output signal each time a differential magnitude of the compared signals has a predetermined value.
Claim 15
Independent Claim
66 words
A method for representing in digital forms durations between amplitude peaks and valleys of an analog time-varying input signal, the method comprising the steps of: delaying the time-varying input signal; comparing the magnitudes of the time-varying input signal and the delayed time-varying input signal; and producing a transition in a digital output signal each time a differential magnitude of the compared signals has a predetermined value.
Claim 16
Dependent Claim
26 words
The method of claim 12 wherein said transition in the digital output signal is produced each time the magnitudes of the compared signals are approximately equal.
Claim 17
Dependent Claim
26 words
The method of claim 12 wherein said transition in the digital output signal is produced each time a reversal in magnitude of the compared signals occurs.
Claim 18
Dependent Claim
35 words
The method of claim 12 wherein the step of delaying comprises delaying the time-varying input signal by an amount less than the time of one-half of the shortest expected cycle of the time-varying input signal.
Claim 19
Dependent Claim
48 words
The method of claim 12 wherein the transition in the digital output signal is produced by subtracting the amplitudes of the time-varying input signal and the delayed time-varying input signal to produce a difference amplitude, and producing said transition each time the sign of the difference amplitude changes.
Claim 20
Dependent Claim
29 words
The method of claim 16 including the step of providing a digital representation of the amplitude of the time-varying input signal at each transition of the digital output signal.
Claim 21
Dependent Claim
43 words
The method of claim 1 including the step of converting the time-varying input signal into a digital input signal comprising a sequence of amplitude samples at regular intervals, and wherein the steps of delaying and comparing are performed on the digital input signal.
Claim 22
Dependent Claim
28 words
The method of claim 12 including the step of storing the time between successive transitions of the digital output signal as one characteristic of the time-varying input signal.
Claim 23
Dependent Claim
67 words
The method of claim 19 including the steps of providing a digital representation of the amplitude of the time-varying input signal at each transition of the digital output signal to produce a sequence of digital amplitude representations corresponding to the amplitudes of the peaks and valleys of the time-varying input signal, and storing the sequence of digital amplitude representations as a characteristic of the time-varying input signal.
Claim 24
Dependent Claim
67 words
The method of claim 12 including the steps of providing a digital representation of the amplitude of the time-varying input signal at each transition of the digital output signal to produce a sequence of digital amplitude representations corresponding to the amplitudes of the peaks and valleys of the time-varying input signal, and storing the sequence of digital amplitude representations as a characteristic of the time-varying input signal.
Claim 25
Dependent Claim
59 words
The method of claim 20 including the step of reconstructing the time-varying input signal in response to the sequence of digital amplitude representations and the transitions in the digital output signal by producing an analog signal level in response to each digital amplitude representation in said sequence thereof at times determined by the transitions in the digital output signal.
Claim 26
Dependent Claim
80 words
A circuit for extracting amplitude information from a time-varying input signal comprising: means for delaying the time-varying input signal by an amount less than one half of the shortest expected cycle thereof; means responsive to the amplitudes of time-varying input signal and the delayed time-varying input signal for producing a digital output signal each time a predetermined relationship exists between said amplitudes; and means for extracting the amplitude of the time-varying input signal in response to said digital output signal.
Claim 27
Dependent Claim
80 words
A circuit for extracting amplitude information from a time-varying input signal comprising: means for delaying the time-varying input signal by an amount less than one half of the shortest expected cycle thereof; means responsive to the amplitudes of time-varying input signal and the delayed time-varying input signal for producing a digital output signal each time a predetermined relationship exists between said amplitudes; and means for extracting the amplitude of the time-varying input signal in response to said digital output signal.
Claim 28
Dependent Claim
35 words
The circuit of claim 23 wherein said means for producing said digital output signal comprises means for comparing said amplitudes, and means for producing said digital output signal each time the amplitudes are approximately equal.
Claim 29
Dependent Claim
39 words
The circuit of claim 23 wherein said means for producing said digital output signal comprises means for comparing said amplitudes, and means for producing said digital output signal each time a reversal in amplitude of the compared amplitudes occurs.
Claim 30
Dependent Claim
29 words
The circuit of claim 25 wherein said extracting means comprises means for selectively providing the amplitude of the delayed time-varying input signal in response to the digital output signal.
Claim 31
Dependent Claim
68 words
The circuit of claim 23 wherein said digital output signal producing means comprises means for comparing the relative amplitudes of said time varying input signal and said delayed time-varying input signal and producing said digital output signal each time a predetermined relationship occurs, and wherein said extracting means comprises means for selectively providing the amplitude of the delayed time-varying input signal in response to the digital output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |