Dynamic strobe timing circuitry for A/D conversion apparatus

Claim 3

Apparatus for dynamically delaying a clock signal to optimize the strobe point in the process of digitizing an analog signal comprising, in combination: conversion first means for A/D converting a multilevel analog signal which analog signal is level representative of a digital value to produce an N+1 bit digital word output signal; comparison second means, connected to said first means to receive said digital word output signal therefrom, for comparing the N most significant bits of the present and previous digital word values for ascertaining the slope of the analog signal, said second means generating an output logical signal indicative of the relative values of said present and previous digital words; OR gate third means, connected to said second means, for exclusive ORing the most significant bit, of the present digital word, that is not used in the comparison, with a given logic value when the present digital word value is greater than the previous digital word value; integration fourth means, connected to said third means for receiving logical output signals therefrom, for integrating the result of the exclusive ORing step; clock fifth means for supplying a clock signal; delay sixth means, connected to said fourth and fifth means for receiving signals therefrom, for variably delaying said clock signal in accordance with the results of the integrating to generate a strobe signal for initiating each A/D conversion; and connection seventh means connecting said sixth means to said first means for providing the strobe signal thereto.

Claim 4

Apparatus for dynamically delaying a clock signal to optimize the strobe point in the process of digitizing an analog signal comprising, in combination: conversion first means for A/D converting a multilevel analog signal which analog signal is level representative of a digital value to produce an N+1 bit digital word output signal; comparison second means, connected to said first means to receive said digital word output signal therefrom, for comparing the N most significant bits of the present and previous digital word values for ascertaining the slope of the analog signal, said second means generating an output logical signal indicative of the relative values of said present and previous digital words; OR gate third means, connected to said second means, for exclusive ORing the most significant bit, of the present digital word, that is not used in the comparison, with a given logic value when the present digital word value is greater than the previous digital word value; integration fourth means, connected to said third means for receiving logical output signals therefrom, for integrating the result of the exclusive ORing step; clock fifth means for supplying a clock signal; delay sixth means, connected to said fourth and fifth means for receiving signals therefrom, for variably delaying said clock signal in accordance with the results of the integrating to generate a strobe signal for initiating each A/D conversion; and connection seventh means connecting said sixth means to said first means for providing the strobe signal thereto.

Claim 5

Apparatus for optimizing the clock timing in a multilevel A/D conversion process comprising, in combination: signal supply first means for supplying an analog signal representing a plurality of discrete signal levels; clock signal second means for supplying a clock signal; analog-to-digital (A/D) third means, including input means connected to said first means for receiving said analog signal therefrom and including strobe signal input means, for converting received analog signal levels at times determined by a received strobe signal to digital output words indicative of said levels; analog signal trajectory detection fourth means, including input means connected to said third means for receiving said digital output words therefrom, for outputting a slope signal indicative of the level of the analog signal last converted by said third means as compared to the level previously converted; logic fifth means, connected to said third and fourth means for receiving signal therefrom, for detecting whether the conversion time of said third means is early or late relative predetermined signal level values and outputting a steering signal in accordance with said detecting; integration sixth means, connected to said fifth means for receiving said steering signal therefrom, for outputting an integrated signal; variable delay seventh means, connected to said second and sixth means for receiving clock and integrated signals therefrom, for outputting a timed delayed version of said clock as a strobe signal to said third means in accordance with said integrated signal.

Claim 6

Apparatus for optimizing the clock timing in a multilevel A/D conversion process comprising, in combination: signal supply first means for supplying an analog signal representing a plurality of discrete signal levels; clock signal second means for supplying a clock signal; analog-to-digital (A/D) third means, including input means connected to said first means for receiving said analog signal therefrom and including strobe signal input means, for converting received analog signal levels at times determined by a received strobe signal to digital output words indicative of said levels; analog signal trajectory detection fourth means, including input means connected to said third means for receiving said digital output words therefrom, for outputting a slope signal indicative of the level of the analog signal last converted by said third means as compared to the level previously converted; logic fifth means, connected to said third and fourth means for receiving signal therefrom, for detecting whether the conversion time of said third means is early or late relative predetermined signal level values and outputting a steering signal in accordance with said detecting; integration sixth means, connected to said fifth means for receiving said steering signal therefrom, for outputting an integrated signal; variable delay seventh means, connected to said second and sixth means for receiving clock and integrated signals therefrom, for outputting a timed delayed version of said clock as a strobe signal to said third means in accordance with said integrated signal.

Claim 9

Apparatus for dynamically delaying a clock signal to optimize the strobe point in the process of digitizing a multilevel analog signal comprising, in combination: A/D conversion first means for converting a multilevel analog signal which analog signal is level representative of a digital value to produce an N bit digital word output signal and a one bit error signal; comparison second means, connected to said first means, for comparing the N most significant bits of the present and previous word values for generating a slope signal logically indicative of the slope of the analog signal; logic third means, connected to said first and second means, for exclusive ORing the one bit error signal with the slope signal; integration fourth means, connected to said third means, for integrating the result of the exclusive ORing step; and delay fifth means, connected to said fourth and first means, for variably delaying a clock signal in accordance with the results of the integrating to generate a strobe signal for initiating each A/D conversion.

Claim 10

Apparatus for dynamically delaying a clock signal to optimize the strobe point in the process of digitizing a multilevel analog signal comprising, in combination: A/D conversion first means for converting a multilevel analog signal which analog signal is level representative of a digital value to produce an N bit digital word output signal and a one bit error signal; comparison second means, connected to said first means, for comparing the N most significant bits of the present and previous word values for generating a slope signal logically indicative of the slope of the analog signal; logic third means, connected to said first and second means, for exclusive ORing the one bit error signal with the slope signal; integration fourth means, connected to said third means, for integrating the result of the exclusive ORing step; and delay fifth means, connected to said fourth and first means, for variably delaying a clock signal in accordance with the results of the integrating to generate a strobe signal for initiating each A/D conversion.