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US5055820A Expired / Lapsed US ⏱️ 0.0 years remaining

Hall element and magnetic sensor system employing the same

Assignee: Mitsubishi Electric Corp
•
Filing: 1990-01-04
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Granted: 1991-10-08
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Expires: 2010-01-04
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Abstract

Abstract A Hall device a semiconductor region embedded in a substrate, the embedded region having opposite main and back surfaces and a pair of side surfaces parallel to and spaced apart from respective ones of the main, back and side surfaces of the substrate. A pair of current electrodes are formed of first highly doped regions embedded in the substrate respectively (i) between the main surfaces of the substrate and the semiconductor region and (ii) between the back surfaces of the substrate and semiconductor region so as to sandwich the semiconductor region between the main and back surfaces of the substrate. A pair of Hall voltage detecting electrodes are formed of second highly doped regions embedded in the substrate, respectively between side surfaces of the substrate and semiconductor region. The substrate can be made of SiO 2 to increase electrical isolation between the electrodes.

Inventors

  • 👤 Masatoshi Kimura
  • 👤 Toshio Kumamoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 17:29
CPC Classifications
H; H10; H10N; H10N52/00; H10N52/101

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 158 words
A Hall device comprising: a semiconductor substrate having a main surface, a back surface opposite said main surface and a pair of opposing side surfaces connected to said main and back surfaces, said Hall device comprising: a semiconductor region embedded in said substrate, said semiconductor region having opposite main and back surfaces and a pair of side surfaces parallel to and spaced apart from respective ones of said main, back and side surfaces of said substrate; a pair of current electrodes constituted by first highly doped regions embedded in said substrate respectively between said main surfaces of said substrate and said semiconductor region and between said back surfaces of said substrate and semiconductor region so as to sandwich said semiconductor region between said main and back surfaces of said substrate; and a pair of Hall voltage detecting electrodes constituted by second highly doped regions embedded in said substrate respectively between side surfaces of said substrate and semiconductor region.
Claim 2
Dependent Claim 158 words
A Hall device comprising: a semiconductor substrate having a main surface, a back surface opposite said main surface and a pair of opposing side surfaces connected to said main and back surfaces, said Hall device comprising: a semiconductor region embedded in said substrate, said semiconductor region having opposite main and back surfaces and a pair of side surfaces parallel to and spaced apart from respective ones of said main, back and side surfaces of said substrate; a pair of current electrodes constituted by first highly doped regions embedded in said substrate respectively between said main surfaces of said substrate and said semiconductor region and between said back surfaces of said substrate and semiconductor region so as to sandwich said semiconductor region between said main and back surfaces of said substrate; and a pair of Hall voltage detecting electrodes constituted by second highly doped regions embedded in said substrate respectively between side surfaces of said substrate and semiconductor region.
Claim 3
Dependent Claim 40 words
A Hall device in accordance with the claim 1, wherein said substrate comprises a semiconductor substrate of a certain conductivity type and said semiconductor region comprises a semiconductor region of a conductivity type opposite to that of the semiconductor substrate.
Claim 4
Dependent Claim 15 words
A Hall device in accordance with claim 1, wherein said substrate comprises SiO 2 substrate.
Claim 5
Dependent Claim 141 words
A Hall device comprising: a SiO 2 substrate having a main surface, a back surface opposite said main surface and first and second pairs of opposing side surfaces connected to said main and back surfaces; a semiconductor region embedded in said SiO 2 substrate having first and second pairs of opposing side surfaces parallel to and spaced apart from respective ones of said first and second pairs of side surfaces of said substrate; a pair of current electrodes constituted by first highly doped regions embedded in said SiO 2 substrate respectively between respective first pairs of side surfaces of said substrate and semiconductor region; and a pair of Hall voltage detecting electrodes constituted by second highly doped regions embedded in said SiO 2 substrate on respective opposing surfaces of said semiconductor region other than on which said current electrodes are provided.
Claim 6
Dependent Claim 141 words
A Hall device comprising: a SiO 2 substrate having a main surface, a back surface opposite said main surface and first and second pairs of opposing side surfaces connected to said main and back surfaces; a semiconductor region embedded in said SiO 2 substrate having first and second pairs of opposing side surfaces parallel to and spaced apart from respective ones of said first and second pairs of side surfaces of said substrate; a pair of current electrodes constituted by first highly doped regions embedded in said SiO 2 substrate respectively between respective first pairs of side surfaces of said substrate and semiconductor region; and a pair of Hall voltage detecting electrodes constituted by second highly doped regions embedded in said SiO 2 substrate on respective opposing surfaces of said semiconductor region other than on which said current electrodes are provided.
Claim 7
Dependent Claim 141 words
A Hall device comprising: a first conductivity type semiconductor substrate having a main surface, a back surface opposite said main surface and a pair of opposing side surfaces connected to said main and back surfaces; a semiconductor region provided in said substrate, said semiconductor region having opposite main and back surfaces and a pair of side surfaces parallel to and spaced apart from respective ones of said main, back and side surfaces of said substrate; a pair of current electrodes constituted by first highly doped regions embedded in said substrate respectively between said main surfaces of said substrate and said semiconductor region and between said back surface of said substrate and semiconductor region; and a pair of Hall voltage detecting electrodes constituted by second highly doped regions embedded in said substrate respectively between side surfaces of said substrate and semiconductor region.
Claim 8
Dependent Claim 141 words
A Hall device comprising: a first conductivity type semiconductor substrate having a main surface, a back surface opposite said main surface and a pair of opposing side surfaces connected to said main and back surfaces; a semiconductor region provided in said substrate, said semiconductor region having opposite main and back surfaces and a pair of side surfaces parallel to and spaced apart from respective ones of said main, back and side surfaces of said substrate; a pair of current electrodes constituted by first highly doped regions embedded in said substrate respectively between said main surfaces of said substrate and said semiconductor region and between said back surface of said substrate and semiconductor region; and a pair of Hall voltage detecting electrodes constituted by second highly doped regions embedded in said substrate respectively between side surfaces of said substrate and semiconductor region.
Claim 9
Dependent Claim 41 words
A Hall device in accordance with claim 1, wherein the length of each said Hall voltage detecting electrodes is equal to the length of said semiconductor region in a direction from said main to said back surface of said semiconductor region.
Claim 10
Dependent Claim 23 words
A Hall device in accordance with claim 1, wherein each said Hall voltage detecting electrodes completely covers side surfaces of said semiconductor region.

References Cited (Backward Citations)

US4584552A Cited
JPS5987884A Cited
JPS62208682A Cited
US4829352A Cited
JPS6361167A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-10-07 1995-04-08 1995-10-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-10-07 1999-04-08 1999-10-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-10-07 2003-04-08 2003-10-08 $7700.00 Window Closed / Lapsed

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