Undershoot reduction circuit

Claim 2

A circuit for reducing negative ground bounce having an input terminal and an output terminal comprising; an output buffer having an input and an output, said input being coupled to the input terminal of the circuit, and said output being coupled to the output terminal of the circuit; a gate circuit having first and second inputs and an output, said first input being coupled to the input terminal of the circuit, and said second input being coupled to the output terminal of the circuit; injector means for providing a predetermined current to the output terminal of the circuit, said injector means includes: a first transistor having first, second and control electrodes, said second electrode being coupled to a first supply voltage terminal, and said control electrode being coupled to said output of said gate circuit; and a second transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said first transistor, said second electrode being coupled to the output terminal of the circuit, and said control electrode being coupled to the input terminal of the circuit.

Claim 3

The circuit according to claim 1 further includes: resistive means coupled between said output of said gate circuit and said control electrode of said first transistor of said injector means for decreasing the rate of a logic transition occurring at said control electrode of said first transistor.

Claim 4

The circuit according to claim 2 further includes: an iverter having an input and an output, said input being coupled to the input terminal of the circuit, and said output being coupled to said control electrode of said second transistor of said injector means.

Claim 5

The circuit according to claim 3 wherein said gate circuit includes: a first transistor having first, second and control electrodes, said second electrode being coupled to said first supply voltage terminal, and said control electrode being coupled to said second input of said gate circuit; a second transistor having first, second and control electrodes, said second electrode being coupled to said first electrode of said first transistor of said gate circuit, and said control electrode being coupled to said first input of said gate circuit; a third transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said second transistor of said gate circuit said second electrode being coupled to a second supply voltage terminal, and said control electrode being coupled to said control electrode of said second transistor of said gate circuit; and a fourth transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said third transistor of said gate circuit, said second electrode being coupled to said second supply voltage terminal, and said control electrode being coupled to said control electrode of said first transistor of said gate circuit.

Claim 6

A circuit for reducing negative ground bounce having an input terminal and an output terminal, comprising; an output buffer having an input and an output, said input being coupled to the input terminal of the circuit, and said output being coupled to the output terminal of the circuit; a gate circuit having first and second inputs and an output, said first input being coupled to the input terminal of the circuit, and said second input being coupled to the output terminal of the circuit; injector means for providing a predetermined current to the output terminal of the circuit, said injector means includes: a first transistor having first, second and control electrodes, said second electrode being coupled to a first supply voltage terminal, and said control electrode being coupled to said output of said gate circuit; and a second transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said first transistor, and said control electrode being coupled to the input terminal of the circuit; and tri-state means responsive to a plurality of enable signals and coupled to said gate circuit and to said second electrode of said second transistor of said injector means for disabling the circuit when said enable signals are in a predetermined logic state.

Claim 7

A circuit for reducing negative ground bounce having an input terminal and an output terminal, comprising; an output buffer having an input and an output, said input being coupled to the input terminal of the circuit, and said output being coupled to the output terminal of the circuit; a gate circuit having first and second inputs and an output, said first input being coupled to the input terminal of the circuit, and said second input being coupled to the output terminal of the circuit; injector means for providing a predetermined current to the output terminal of the circuit, said injector means includes: a first transistor having first, second and control electrodes, said second electrode being coupled to a first supply voltage terminal, and said control electrode being coupled to said output of said gate circuit; and a second transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said first transistor, and said control electrode being coupled to the input terminal of the circuit; and tri-state means responsive to a plurality of enable signals and coupled to said gate circuit and to said second electrode of said second transistor of said injector means for disabling the circuit when said enable signals are in a predetermined logic state.

Claim 8

The circuit according to claim 5 further includes: resistive means coupled between said output of said gate circuit and said control electrode of said first transistor for decreasing the rate of a logic transition occurring at said control electrode of said first transistor of said injector means.

Claim 9

The circuit according to claim 6 further includes: an inverter having an input and an output, said input being coupled to the input terminal of the circuit, and said output being coupled to said control electrode of said second transistor of said injector means.

Claim 10

The circuit according to claim 7 wherein said tri-state means includes: a first transistor having first, second and control electrodes, said first electrode being coupled to said gate circuit, said second electrode being coupled to said first supply voltage terminal, and said control electrode being coupled to a first one of said plurality of enable signals; and a second transistor having first, second and control electrodes, said first electrode being coupled to said second electrode of said second transistor of said injector means, said second electrode being coupled to the output terminal of the circuit, and said control electrode being coupled to said second one of said plurality of enable signals.

Claim 11

The circuit according to claim 8 wherein said gate circuit includes: a first transistor having first, second and control electrodes, said second electrode being coupled to said first electrode of said first transistor of said tri-state means, and said control electrode being coupled to said second input of said gate circuit; a second transistor having first, second and control electrodes, said second electrode being coupled to said first electrode of said first transistor of said gate circuit, and said control electrode being coupled to said first input of said gate circuit; a third transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said second transistor of said gate circuit, said second electrode being coupled to a second supply voltage terminal, and said control electrode being coupled to said control electrode of said second transistor of said gate circuit; and a fourth transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said third transistor of said gate circuit, said second electrode being coupled to said second supply voltage terminal, and said control electrode being coupled to said control electrode of said first transistor of said gate circuit.

Claim 12

A circuit for reducing negative ground bounce having an input signal applied at an input terminal thereof and an output signal supplied at an output terminal thereof, comprising; an output buffer having an input and an output, said input being responsive to the input signal, and said output being coupled to the output terminal of the circuit for providing the output signal; gate means having first and second inputs responsive to the input signal and the output signal for providing a control signal at an output thereof, said control signal being in a first logic state when the input signal and the output signal are in predetermined logic states; and injector means responsive to said control signal and to the input signal for providing a predetermined current to the output terminal of the circuit wherein said injector current decreases the negative peak undershoot voltage occurring in a ground reference of the circuit.

Claim 13

A circuit for reducing negative ground bounce having an input signal applied at an input terminal thereof and an output signal supplied at an output terminal thereof, comprising; an output buffer having an input and an output, said input being responsive to the input signal, and said output being coupled to the output terminal of the circuit for providing the output signal; gate means having first and second inputs responsive to the input signal and the output signal for providing a control signal at an output thereof, said control signal being in a first logic state when the input signal and the output signal are in predetermined logic states; and injector means responsive to said control signal and to the input signal for providing a predetermined current to the output terminal of the circuit wherein said injector current decreases the negative peak undershoot voltage occurring in a ground reference of the circuit.

Claim 14

The circuit according to claim 10 wherein said injector means includes: a first transistor having first, second and control electrodes, said second electrode being coupled to a first supply voltage terminal, and said control electrode being coupled to said output of said gate means; and a second transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said first transistor of said injector means, said second electrode being coupled to the output terminal of the circuit, and said control electrode being coupled to the input terminal of the circuit.

Claim 15

The circuit according to claim 11 further includes: resistive means coupled between said output of said gate means and said control electrode of said first transistor of said injector means for decreasing the rate of a logic transition occurring at said control electrode of said first transistor of said injector means.

Claim 16

The circuit according to claim 12 further includes: an inverter having an input and an output, said input being coupled to the input terminal of the circuit, and said output being coupled to said control electrode of said second transistor of said injector means.

Claim 17

The circuit according to claim 13 wherein said gate means includes: a first transistor having first, second and control electrodes, said second electrode being coupled to said first supply voltage terminal, and said control electrode being coupled to said second input of said gate means; a second transistor having first, second and control electrodes, said second electrode being coupled to said first electrode of said first transistor of said gate means, and said control electrode being coupled to said first input of said gate means; a third transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said second transistor of said gate means, said second electrode being coupled to a second supply voltage terminal, and said control electrode being coupled to said control electrode of said second transistor of said gate means; and a fourth transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said third transistor of said gate means, said second electrode being coupled to said second supply voltage terminal, and said control electrode being coupled to said control electrode of said first transistor of said gate means.