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US4970419A Expired / Lapsed US ⏱️ 0.0 years remaining

Low-noise transmission line termination circuitry

Assignee: Unisys Corp
•
Filing: 1987-03-23
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Granted: 1990-11-13
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Expires: 2007-03-23
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Abstract

Abstract Transmission line termination circuitry is provided on a driven IC chip utilizing active transistors constructed and arranged so as to steer appropriately directed damping currents into the input bus in a manner which effectively minimizes both overshoot and undershoot without making undue demands on the normally provided chip power supply.

Inventors

  • 👤 Timothy P. Hagen
  • 👤 Paul G. Tumms

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 11:04
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K17/00; H03K17/16

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 219 words
For use in a computer circuit, the combination comprising: an integrated circuit chip having an input for receiving a binary input signal; and transmission line termination circuitry included on said integrated circuit chip and coupled to said input for reducing noise occurring when a binary signal is transmitted to said input; said transmission line termination circuitry comprising a first constant current source, a second constant current source, and a switchable current steering switch, said first current source being coupled to said input so as to provide a DC load at said input for an applied signal, and said second current source being coupled to said input via said switchable current steering switch for setting clamping current for a transition of said binary signal; said first current source including a first transistor coupled between a current supply voltage and said input, said second current source including a second transistor coupled between said current supply voltage and said current switch, and each of said first and second transistors including a control terminal coupled to a control voltage source; said switchable current steering switch being operative to switch in response to said binary input signal rising to a predetermined level so as to cause the input signal to see a step increase in load current as it increases above said predetermined level.
Claim 2
Dependent Claim 219 words
For use in a computer circuit, the combination comprising: an integrated circuit chip having an input for receiving a binary input signal; and transmission line termination circuitry included on said integrated circuit chip and coupled to said input for reducing noise occurring when a binary signal is transmitted to said input; said transmission line termination circuitry comprising a first constant current source, a second constant current source, and a switchable current steering switch, said first current source being coupled to said input so as to provide a DC load at said input for an applied signal, and said second current source being coupled to said input via said switchable current steering switch for setting clamping current for a transition of said binary signal; said first current source including a first transistor coupled between a current supply voltage and said input, said second current source including a second transistor coupled between said current supply voltage and said current switch, and each of said first and second transistors including a control terminal coupled to a control voltage source; said switchable current steering switch being operative to switch in response to said binary input signal rising to a predetermined level so as to cause the input signal to see a step increase in load current as it increases above said predetermined level.
Claim 3
Dependent Claim 68 words
The invention in accordance with claim 1, wherein said switchable current steering switch includes a third transistor coupled between said second transistor and a switching voltage and a fourth transistor coupled between said second current supply voltage and said input, and wherein said third transistor and said fourth transistor each include a control terminal coupled to a reference voltage chosen based on the levels of said binary signal.
Claim 4
Dependent Claim 14 words
The invention in accordance with claim 2, wherein said switching voltage is circuit ground.
Claim 5
Dependent Claim 41 words
The invention i accordance with claim 2, wherein said circuit means additionally includes a fifth transistor coupled between said switching voltage and said input for providing falling edge clamping, said fifth transistor including a control terminal coupled to said reference voltage.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-11-12 1994-05-14 1994-11-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-11-12 1998-05-14 1998-11-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-11-12 2002-05-14 2002-11-13 $7700.00 Window Closed / Lapsed

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