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US5052031A
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Phase locked loop including non-integer multiple frequency reference signal
Assignee: Nokia Bell Labs
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Filing: 1990-08-14
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Granted: 1991-09-24
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Expires: 2010-08-14
Abstract
Abstract A digital phase locked loop is employed to realize an output clock signal from a reference signal having a frequency which is not an integer multiple of the output clock signal frequency. This is realized by employing a programmable divider for dividing the reference signal which is dynamically controlled by a controllably variable base divisor. The base divisor control is responsive to the reference signal and to a phase error signal. The base divisor is generated to obtain a desired fractional division of the reference signal frequency and in a manner to minimize the amplitude of any resulting "high" frequency jitter in the output clock signal from the loop.
Inventors
- 👤 Nicholas J. Molloy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:47
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/076
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
138 words
A digital phase locked loop for generating an output clock signal having a prescribed frequency comprising: a source of a first reference clock signal; means supplied with said output clock signal for generating a phase clock signal; phase detector means responsive to said first reference clock signal and said phase clock signal for generating an error signal; means supplied with said error signal for generating a control signal representative of a filtered version of said error signal; a source of a reference signal having a frequency which is a non-integer multiple of said output clock signal frequency; programmable divider means responsive to a divisor control signal for dividing said reference signal to obtain said output clock signal having said prescribed frequency; and means supplied with said reference signal and said contol signal for generating said divisor control signal.
Claim 2
Dependent Claim
138 words
A digital phase locked loop for generating an output clock signal having a prescribed frequency comprising: a source of a first reference clock signal; means supplied with said output clock signal for generating a phase clock signal; phase detector means responsive to said first reference clock signal and said phase clock signal for generating an error signal; means supplied with said error signal for generating a control signal representative of a filtered version of said error signal; a source of a reference signal having a frequency which is a non-integer multiple of said output clock signal frequency; programmable divider means responsive to a divisor control signal for dividing said reference signal to obtain said output clock signal having said prescribed frequency; and means supplied with said reference signal and said contol signal for generating said divisor control signal.
Claim 3
Dependent Claim
49 words
A digital phase locked loop as defined in claim 1 wherein said means for generating said divisor control signal includes means for controllably dividing said reference signal to obtain a divisor signal and means for combining said divisor signal and said control signal to obtain said divisor control signal.
Claim 4
Dependent Claim
44 words
A digital phase locked loop as defined in claim 2 wherein said means for controllably dividing includes means for generating a prescribed sequence of divisor signals so that any resulting jitter is at a high frequency of acceptable amplitude in said output clock signal.
Claim 5
Dependent Claim
36 words
A digital phase locked loop as defined in claim 3 wherein said means for generating a prescribed sequence of divisor signals generates at least two divisor signals which alternate in said sequence in a predetermined manner.
Claim 6
Dependent Claim
43 words
A digital phase locked loop as defined in claim 4 wherein said means for generating said sequence of at least two divisor signals alternates said at least two divisor signals in a predetermined uniform manner so that said output clock frequency is obtained.
Claim 7
Dependent Claim
52 words
A digital phase locked loop as defined in claim 5 wherein said means for generating said phase clock signal includes a source of gapped signal information and controllable divider means supplied with said output clock signal and being responsive to said gapped signal information for controllably adjusting said phase clock signal rate.
Claim 8
Dependent Claim
50 words
A digital phase locked loop as defined in claim 6 wherein said source of a first reference clock signal includes a source of a reference clock signal in synchronization with a gapped incoming signal and divider means for dividing said reference clock signal to obtain said first reference clock signal.
Claim 9
Dependent Claim
30 words
A digital phase locked loop as defined in claim 7 wherein said at least two divisors include a first divisor of 33 and at least a second divisor of 34.
Claim 10
Dependent Claim
76 words
A digital phase locked loop as defined in claim 8 wherein said nominal frequency includes 193 time intervals and wherein said sequence of said first divisor and said at least second comprises starting with said at least second divisor alternate every time interval between said at least second divisor and said at least first divisor, every sixth time interval said-at least second divisor is repeated except in time intervals 66, 126 and 192 alternate said divisors.
Claim 11
Dependent Claim
42 words
A digital phase locked loop as defined in claim 9 wherein said reference signal has a frequency of 51.84 MHz, said output clock signal has a nominal frequency of 1.544 MHz and said reference clock signal has a frequency of 1.728 MHz.
Claim 12
Dependent Claim
28 words
A digital phase locked loop as defined in claim 2 wherein said means for controllably dividing includes means for obtaining a prescribed fractional division of said reference signal.
Claim 13
Dependent Claim
48 words
A digital phase locked loop as defined in claim 11 wherein said means for obtaining a prescribed fractional division includes means for generating at least two divisors which alternate in a prescribed sequence at a rate in prescribed relationship to a nominal frequency of said output clock signal.
Claim 14
Dependent Claim
52 words
A digital phase locked loop as defined in claim 12 wherein said means for generating said at least two divisors alternates them as often as possible and in as uniform a manner as possible so that any resulting jitter is at a high frequency of acceptable amplitude in said output clock signal.
Claim 15
Dependent Claim
30 words
A digital phase locked loop as defined in claim 13 wherein said at least two divisors include a first divisor of 33 and at least a second divisor of 34.
Claim 16
Dependent Claim
77 words
A digital phase locked loop as defined in claim 14 wherein said nominal frequency includes 193 time intervals and wherein said sequence of said first divisor and said at least second comprises starting with said at least second divisor alternate every time interval between said at least second divisor and said at least first divisor, every sixth time interval said at least second is divisor repeated except in time intervals 66, 126 and 192 alternate said divisors.
Claim 17
Dependent Claim
42 words
A digital phase locked loop as defined in claim 15 wherein said reference signal has a frequency of 51.84 MHz, said output clock signal has a nominal frequency of 1.544 MHz and said reference clock signal has a frequency of 1.728 MHz.
References Cited (Backward Citations)
US3943460A
Cited
US3936762A
Cited
US4030045A
Cited
US4363002A
Cited
US4538119A
Cited
US4847875A
Cited
US4903283A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-23 | 1995-03-25 | 1995-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-23 | 1999-03-25 | 1999-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-23 | 2003-03-25 | 2003-09-24 | $7700.00 | Window Closed / Lapsed |