Patent US5051746A successfully refreshed from Google Patents.
US5051746A
Expired / Lapsed
US
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Interpolation circuit for use in an A/D converter
Assignee: US Philips Corp
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Filing: 1990-03-22
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Granted: 1991-09-24
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Expires: 2010-03-22
Abstract
Abstract An interpolation circuit for an A/D converter comprises a first and a second pair of inputs (2, 2'; 3, 3') and at least three pairs of outputs (20, 20'; 24, 24'; 21, 21'). The pairs of inputs receive pairs of two input signals (V 1 , V 1c , V 5 , V 5c ) which are substantially complementary to one another. At least two pairs of outputs (20, 20'; 24, 24') supply pairs of two substantially complementary output signals. A first output (21) of the third pair of outputs (21, 21') is coupled to a first input (2) of the first pair of inputs (2, 2'). The second output (21') of the third pair of outputs is connected to a circuit node other than one of the inputs of the first pair of inputs. This node may be, for example, the first input (3') of the second pair of inputs (FIG. 9). Another possibility is to make the node one end (38) of an impedance element (32) which has its other end coupled to the second input (2') of the first pair of inputs (FIG. 3).
Inventors
- 👤 Robert E. J. Van de Grift
- 👤 Martien van der Veen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:21
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/30; H; H03; H03M; H03M1/00; H03M1/12; H03M1/20; H03M1/202; H03M1/203; H03M1/204; H03M1/205; H03M1/14; H03M1/141
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
130 words
An interpolation circuit comprising: a first and a second pair of inputs with each pair of inputs receiving two complementary input signals having edges with finite slopes, at least three pairs of outputs with each of at least two pairs of said outputs supplying two output signals which are substantially complementary to one another, the first pair of outputs being connected to the first pair of inputs and the second pair of outputs being connected to the second pair of inputs, means connecting a first output of the third pair of outputs to a circuit node other than one of the inputs of the first pair of inputs, and means connecting a second output of the third pair of outputs to a first input of the first pair of inputs.
Claim 2
Dependent Claim
130 words
An interpolation circuit comprising: a first and a second pair of inputs with each pair of inputs receiving two complementary input signals having edges with finite slopes, at least three pairs of outputs with each of at least two pairs of said outputs supplying two output signals which are substantially complementary to one another, the first pair of outputs being connected to the first pair of inputs and the second pair of outputs being connected to the second pair of inputs, means connecting a first output of the third pair of outputs to a circuit node other than one of the inputs of the first pair of inputs, and means connecting a second output of the third pair of outputs to a first input of the first pair of inputs.
Claim 3
Dependent Claim
45 words
An interpolation circuit as claimed in claim 1 wherein said third pair of outputs supply a non-complementary pair of interpolation output signals determined by the input signal at the first input of the first pair of inputs and by a signal at said circuit node.
Claim 4
Dependent Claim
22 words
An interpolation circuit as claimed in claim 2 wherein said circuit node comprises a first input of the second pair of inputs.
Claim 5
Dependent Claim
22 words
An interpolation circuit as claimed in claim 1 wherein said circuit node comprises a first input of the second pair of inputs.
Claim 6
Dependent Claim
56 words
An interpolation circuit as claimed in claim 1 further comprising at least first and second series connected impedance elements coupled between one input of said first pair of inputs and one input of said second pair of inputs, and wherein said circuit node comprises a junction point between said first and second series connected impedance elements.
Claim 7
Dependent Claim
104 words
An interpolation circuit as claimed in claim 2 further comprising at least first and second series connected impedance elements coupled between one input of said first pair of inputs and one input of said second pair of inputs, wherein said circuit node comprises a junction point between said first and second series connected impedance elements, a fourth pair of outputs for supplying a pair of non-complementary output signals, means connecting a first output of the fourth pair of outputs to said circuit node, and means connecting a second output of the fourth pair of outputs to one input of said second pair of inputs.
Claim 8
Dependent Claim
157 words
An interpolation circuit as claimed in claim 2 further comprising at least first and second series connected impedance elements coupled between one input of said first pair of inputs and one input of said second pair of inputs, wherein said circuit node comprises a junction point between said first and second series connected impedance elements, at least third and fourth series connected impedance elements coupled between the other input of said first pair of inputs and the other input of said second pair of inputs, a fourth pair of outputs for supplying a pair of non-complementary output signals, means connecting a first output of the fourth pair of outputs to a circuit node between said third and fourth series connected impedance elements, and means connecting a second output of the fourth pair of outputs to one input of the second pair of inputs or to said circuit node between the first and second series connected impedance elements.
Claim 9
Dependent Claim
60 words
An interpolation circuit as claimed in claim 7 wherein said first, second, third and fourth impedance elements comprise first, second, third and fourth resistors, respectively, and with the resistance values of the first and second resistors in the ratio of 2R to R and the resistance values of the third and fourth resistors in the ratio of 2R to R.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-23 | 1995-03-25 | 1995-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-23 | 1999-03-25 | 1999-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-23 | 2003-03-25 | 2003-09-24 | $7700.00 | Window Closed / Lapsed |