Patent US5049513A successfully refreshed from Google Patents.
US5049513A
Expired / Lapsed
US
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Bi CMOS/SOI process flow
Assignee: Texas Instruments Inc
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Filing: 1990-09-17
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Granted: 1991-09-17
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Expires: 2010-09-17
Abstract
Abstract The invention provides a bipolar transistor structure on a buried oxide layer for use in an integrated circuit and a method for fabricating the same. The invention may be incorporated into a method for fabricating bipolar transistors in a BiCMOS structure. The bipolar transistor is constructed in two stacked epitaxial layers. The first epitaxial layer is used to form both the MOSFET and the buried collector of the bipolar transistor. The second epitaxial layer is grown as a blanket epitaxial layer. The intrinsic collector and the base of the bipolar transistor are formed in the second epitaxial layer. An oxide layer is formed over the base. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the second epitaxial layer.
Inventors
- 👤 Robert H. Eklund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:58
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/041; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D86/00; H10D86/201; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/021; H10W10/061; H10W10/10; H10W10/181; H10W10/20; Y; Y10; Y10S; Y10S148/00; Y10S148/009; Y10S148/15
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
189 words
A method of fabricating a bipolar transistor and a CMOS transistor on an SOI substrate, said method comprising: a forming a first epitaxial layer on the surface of the SOI substrate, said epitaxial layer having a bipolar transistor region and a CMOS transistor region; b forming a resist patterned in the inverse of the buried collector over said first epitaxial layer; c forming a buried collector in said bipolar region of said first epitaxial layer; d growing a blanket second epitaxial layer over the first epitaxial layer; e forming an oxide layer over said second epitaxial layer; f forming an emitter opening in the oxide layer; g depositing a polysilicon layer; and h patterning an emitter contact in said polysilicon layer on said opening in the oxide layer and overlapping said oxide layer, whereby the oxide layer over said second epitaxial layer serves as an etch stop for the emitter etch, and whereby the process can use standard SOI CMOS and bulk BICMOS processes and has the advantage of eliminating the isolation problems encountered in a bulk BICMOS process, and whereby the buried n+ collector reduces the collector resistance.
Claim 2
Independent Claim
189 words
A method of fabricating a bipolar transistor and a CMOS transistor on an SOI substrate, said method comprising: a forming a first epitaxial layer on the surface of the SOI substrate, said epitaxial layer having a bipolar transistor region and a CMOS transistor region; b forming a resist patterned in the inverse of the buried collector over said first epitaxial layer; c forming a buried collector in said bipolar region of said first epitaxial layer; d growing a blanket second epitaxial layer over the first epitaxial layer; e forming an oxide layer over said second epitaxial layer; f forming an emitter opening in the oxide layer; g depositing a polysilicon layer; and h patterning an emitter contact in said polysilicon layer on said opening in the oxide layer and overlapping said oxide layer, whereby the oxide layer over said second epitaxial layer serves as an etch stop for the emitter etch, and whereby the process can use standard SOI CMOS and bulk BICMOS processes and has the advantage of eliminating the isolation problems encountered in a bulk BICMOS process, and whereby the buried n+ collector reduces the collector resistance.
Claim 3
Dependent Claim
50 words
The method of claim 1, wherein said method utilizes forming a thick oxide layer at one portion of said second epitaxial layer and a deep collector contact at a second portion of said second epitaxial layer said thick oxide layer being between said emitter opening and said deep collector contact.
Claim 4
Dependent Claim
14 words
The method of claim 2, wherein said emitter polysilicon partially overlays said thick oxide.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein a moat pattern is formed and a silicon etch is performed to isolate device regions.
Claim 6
Dependent Claim
20 words
The method of claim 4, wherein said silicon etch to isolate device regions is performed after said second epitaxial growth.
Claim 7
Dependent Claim
50 words
The method of claim 1, wherein a CMOS transistor is formed in said CMOS transistor region, and wherein said forming an oxide layer over said second epitaxial layer also forms an oxide layer on said CMOS region and wherein said patterning of said polysilicon layer also patterns a poly gate.
Claim 8
Dependent Claim
38 words
The method of claim 1, wherein said emitter contact overlaps said oxide layer, whereby said oxide serves as an insulator between the emitter poly and an extrinsic base, and also as an etch stop for the emitter etch.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-16 | 1995-03-18 | 1995-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-16 | 1999-03-18 | 1999-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-16 | 2003-03-18 | 2003-09-17 | $7700.00 | Window Closed / Lapsed |