US5048022A
Expired / Lapsed
US
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Memory device with transfer of ECC signals on time division multiplexed bidirectional lines
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-08-01
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Granted: 1991-09-10
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Expires: 2009-08-01
Abstract
Abstract A memory for storing data in a computer system. Integrity of data transferred to or from a memory array is monitored by transferring two sets of EDC or ECC data corresponding to a longword of data between the memory array and two separate memory controllers. The probability of an undetected error is very low because the two sets of EDC or ECC data are compared to ensure that they match. The number of lines and pins used is minimized by multiplexing the EDC or ECC data with address signals and cycle type signals. The address and cycle type signals are placed on the time division multiplexed bidirectional lines at the beginning of a memory transfer cycle, and the EDC or ECC data is placed on these time division multiplexed lines at times when a longword of data is being transferred on a set of bidirectional data lines.
Inventors
- 👤 Thomas D. Bissett
- 👤 Norbert H. Riegelhaupt
- 👤 Mitch Berkson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:41
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044; G06F11/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
297 words
A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory, and wherein the memory comprises: memory array means including a plurality of addressable storage locations, for storing data and ECC signals; sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the cycle timing signals; data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the memory transfer cycle; control buffer means, coupled to the plurality to time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring address signals, provided on the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the memory array means, to access the addressable storage locations in the memory array means specified by the address signals, when enabled by sequence timing signals at the beginning of the memory transfer cycle; and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
Claim 2
Dependent Claim
297 words
A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory, and wherein the memory comprises: memory array means including a plurality of addressable storage locations, for storing data and ECC signals; sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the cycle timing signals; data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the memory transfer cycle; control buffer means, coupled to the plurality to time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring address signals, provided on the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the memory array means, to access the addressable storage locations in the memory array means specified by the address signals, when enabled by sequence timing signals at the beginning of the memory transfer cycle; and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
Claim 3
Dependent Claim
304 words
A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory and wherein the memory comprises: memory array means including a plurality of addressable storage locations, for storing data and ECC signals; sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the cycle timing signals; data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the memory transfer cycle; control buffer means, coupled to the plurality of time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring cycle type signals, provided on the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the control buffer means, to enable reading or writing of data in accordance with the type of memory transfer cycle specified by the cycle type signals, when enabled by sequence timing signals at the beginning of the memory transfer cycle; and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
Claim 4
Dependent Claim
304 words
A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory and wherein the memory comprises: memory array means including a plurality of addressable storage locations, for storing data and ECC signals; sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the cycle timing signals; data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the memory transfer cycle; control buffer means, coupled to the plurality of time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring cycle type signals, provided on the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the control buffer means, to enable reading or writing of data in accordance with the type of memory transfer cycle specified by the cycle type signals, when enabled by sequence timing signals at the beginning of the memory transfer cycle; and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
Claim 5
Dependent Claim
371 words
A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory, and wherein the memory comprises: memory array means including a plurality of addressable storage locations, for storing data and ECC signals; sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the cycle timing signals; data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the memory transfer cycle; control buffer means, coupled to the plurality of time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring cycle type signals, provided on a first portion of the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the control buffer means, to enable reading or writing of data in accordance with the type of memory transfer cycle specified by the cycle type signals, when enabled by sequence timing signals at the beginning of the memory transfer cycle; for transferring address signals, provided on a second portion of the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the memory array means, to access the addressable storage locations in the memory array means specified by the address signals, when enabled by sequence timing signals at the beginning of the memory transfer cycle; and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
Claim 6
Dependent Claim
371 words
A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory, and wherein the memory comprises: memory array means including a plurality of addressable storage locations, for storing data and ECC signals; sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the cycle timing signals; data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the memory transfer cycle; control buffer means, coupled to the plurality of time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring cycle type signals, provided on a first portion of the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the control buffer means, to enable reading or writing of data in accordance with the type of memory transfer cycle specified by the cycle type signals, when enabled by sequence timing signals at the beginning of the memory transfer cycle; for transferring address signals, provided on a second portion of the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the memory array means, to access the addressable storage locations in the memory array means specified by the address signals, when enabled by sequence timing signals at the beginning of the memory transfer cycle; and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-09 | 1995-03-11 | 1995-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-09 | 1999-03-11 | 1999-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-09 | 2003-03-11 | 2003-09-10 | $7700.00 | Window Closed / Lapsed |