Patent US5046064A successfully refreshed from Google Patents.
US5046064A
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Packet switching system
Assignee: NEC Corp
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Filing: 1990-01-26
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Granted: 1991-09-03
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Expires: 2010-01-26
Abstract
Abstract A switching system transfers information cells from time positions on incoming TDM channels to selected time positions on a particular outgoing TDM channel. Each information cell contains an address which controls the switching and data which is the transmitted message. A first time buffer delays the incoming information cell from the time position which in occupies on the incoming channel to a time position which is appropriate for the switching. After a switching, a second time buffer delays the outgoing signal unit the time position designated by the address. The alignments of the time positions on the outgoing channels are such that there is no conflict if a plurality of switching systems simultaneously feed information cells to the same outgoing channel.
Inventors
- 👤 Toshio Suzuki
- 👤 Atsuo Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:07
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/106; H04L2012/5638; H04L2012/5646; H04L2012/5649; H04L2012/5672
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
513 words
A packet switching network for receiving information packets on a plurality of input lines, each of said packets having a fixed bit length and consisting of data and an address indicative of a destination of said data, switching said packets responsive to said addresses so that said data are sent to desired destinations, and sending said switched packets via a plurality of output lines, said network comprising: a plurality of time division lines each being associated with a respective one of a plurality of input lines and having a time division multiplex channel, each of the channels being associated with a respective one of a plurality of output lines; a plurality of serial-to-parallel converting means, each of said serial-to-parallel converting means being associated with a respective one of the input lines for delivering an input packets to an associated one of said time division lines; a plurality of address filter means, each of said filter means being associated with a respective one of the input lines for identifying one of the output lines to which a packet is destined on a basis of the address of said packet and for indicating a channel position associated with said one output line on an associated one of said time division lines; a plurality of rearranging means, each rearranging means being associated with a respective one of the input lines for rearranging each packet on a time division multiplex channel in response to an indication from an associated one of said address filter means, said packet being outputted at a particular channel position that is assigned to said packet in response to said rearrangement, and delivering said rearranged packet to an associated one of said time division lines, each of said rearranging means comprising buffer means for temporarily storing an output of an associated one of said serial-to-parallel converting means and, in response to a command from an associated one of said filter means, delivering said stored output to an associated one of said time division lines while delaying said stored output; a plurality of selector means, each of said selector means being associated with a respective one of the output lines and being connected to a plurality of said time division lines for periodically selecting and outputting packets on associated ones of said time division lines; and a plurality of parallel-to-serial converting means, each of said parallel-to-serial converting means being associated with a respective one of the output lines for delivering the packet selected by the associated one of said selector means; each of the time division lines having a bus-connection construction for being terminated respectively at corresponding ones of input terminals of all of the selector means to input the same packet to all of the selector means; all of said time division lines being related with respect to channel positions so that only a single channel that corresponds to one of the output lines exists at any one position on a time division multiplex channel, whereby the packets to be fed out to the same output are prevented from conflicting with each other.
Claim 2
Dependent Claim
513 words
A packet switching network for receiving information packets on a plurality of input lines, each of said packets having a fixed bit length and consisting of data and an address indicative of a destination of said data, switching said packets responsive to said addresses so that said data are sent to desired destinations, and sending said switched packets via a plurality of output lines, said network comprising: a plurality of time division lines each being associated with a respective one of a plurality of input lines and having a time division multiplex channel, each of the channels being associated with a respective one of a plurality of output lines; a plurality of serial-to-parallel converting means, each of said serial-to-parallel converting means being associated with a respective one of the input lines for delivering an input packets to an associated one of said time division lines; a plurality of address filter means, each of said filter means being associated with a respective one of the input lines for identifying one of the output lines to which a packet is destined on a basis of the address of said packet and for indicating a channel position associated with said one output line on an associated one of said time division lines; a plurality of rearranging means, each rearranging means being associated with a respective one of the input lines for rearranging each packet on a time division multiplex channel in response to an indication from an associated one of said address filter means, said packet being outputted at a particular channel position that is assigned to said packet in response to said rearrangement, and delivering said rearranged packet to an associated one of said time division lines, each of said rearranging means comprising buffer means for temporarily storing an output of an associated one of said serial-to-parallel converting means and, in response to a command from an associated one of said filter means, delivering said stored output to an associated one of said time division lines while delaying said stored output; a plurality of selector means, each of said selector means being associated with a respective one of the output lines and being connected to a plurality of said time division lines for periodically selecting and outputting packets on associated ones of said time division lines; and a plurality of parallel-to-serial converting means, each of said parallel-to-serial converting means being associated with a respective one of the output lines for delivering the packet selected by the associated one of said selector means; each of the time division lines having a bus-connection construction for being terminated respectively at corresponding ones of input terminals of all of the selector means to input the same packet to all of the selector means; all of said time division lines being related with respect to channel positions so that only a single channel that corresponds to one of the output lines exists at any one position on a time division multiplex channel, whereby the packets to be fed out to the same output are prevented from conflicting with each other.
Claim 3
Dependent Claim
58 words
A network as claimed in claim 1, wherein each of said address filter means is constructed to deliver the same packet to two or more of the output lines by applying, while said same packet is stored in said buffer means, a cell output command to two or more of said channel positions of said time division lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |