System for changing priority of information

Claim 1

A system for switching information packets between entering time multiplex lines and outgoing time multiplex lines, said packets having two levels of semantic priority assigned thereto, buffer memory means, queueing file means, a storage address of a packet in said buffer memory means being stored in said queueing file means associated with each of said outgoing time multiplex lines designated to transmit the packets, said system comprising a field point memory for words having as many bits as there are outgoing time multiplex lines, the addresses of said field point memory corresponding to the address of said buffer memory means, each bit of said words being at "1" when the packets stored at the same address as said words and designated for an outgoing time multiplex line correspond to a high level semantic priority has not yet been transmitted by an outgoing multiplex line, each packet storage address being chosen from an address of the field point memory where all bits of said words are "0".

Claim 2

A system for switching information packets between entering time multiplex lines and outgoing time multiplex lines, said packets having two levels of semantic priority assigned thereto, buffer memory means, queueing file means, a storage address of a packet in said buffer memory means being stored in said queueing file means associated with each of said outgoing time multiplex lines designated to transmit the packets, said system comprising a field point memory for words having as many bits as there are outgoing time multiplex lines, the addresses of said field point memory corresponding to the address of said buffer memory means, each bit of said words being at "1" when the packets stored at the same address as said words and designated for an outgoing time multiplex line correspond to a high level semantic priority has not yet been transmitted by an outgoing multiplex line, each packet storage address being chosen from an address of the field point memory where all bits of said words are "0".

Claim 6

A system in accordance with any one of the claims 1-4 further including means for storing the storage address in each of the queueing file means, said storage address being accompanied by a first bit defining the semantic priority level of the packet, at least one waiting file comprising two zones in series between an input and an output, means for writing in a first of said two zones only when a second of said two zones is full, said first zone being accessible only to high level semantic priority packets, and means effective between two readings of each file for destroying the oldest read addresses of low semantic level priority packets which were stored earlier than the read address of a high level semantic prioritized packets, the destroyed oldest read addresses being equal in number to a maximum number of read addresses stored in the first zone.

Claim 7

A system in accordance with any one of the claims 1-4 for switching information packets having assigned levels of both semantic and timing priorities, said system further including means for storing the storage address in each queueing file means accompanied by a first bit defining the semantic priority level of the packet and a second bit defining the timing priority level of the packet, each queueing file means being comprised of two files, means for storing in the first file or in the second file responsive to the second bit, the first file storing all the packets with the high timing priority level and the second file being read only when the first file is empty.

Claim 8

A system in accordance with any one of the claims 1-4 and a test memory, a bit in said test memory corresponding to each word of the field point memory, said bit being a "1" when the corresponding word contains at least one bit at a "1" level, said test memory being read at a rate which is slight lower than the average frequency of a period of time during which the packets stay in the buffer memory means, an address file, the reading of a "1" bit in the test memory causing the writing of the address of a word corresponding to the field point memory into the address file.

Claim 9

A system in accordance with any of claims 1-4, further comprising an outgoing time multiplex line scanner, the field point memory having a data input connected to write enable selection wires of a storage address in the queueing file means, said selection wires being active during a first half byte duration, one bit write enable input being also connected to said selection wires and to the output of the outgoing time multiplex line scanner, a label translation memory, a first multiplexer, the scanner being enabled during the first bit period, the enabling being via first AND gates which individually pass the semantic priority bit coming from said label translation memory either at the output of the queueing file means being scanned or at an address input connected to the output of the first multiplexer, a binary cyclic counter, a second multiplexer, an address file, a first input of said first multiplexer being connected to the output of said binary cyclical counter and a second input of said first multiplexer being connected to the output of said second multiplexer, said second multiplexer having a first input which is connected to a data output of the queueing file means and having a second input connected to the output of the address file, the first multiplexer being controlled by said semantic priority bit and the second multiplexer being controlled during a second half byte period, and a data output connected to corresponding inputs of a NAND gate having an output connection to the write enable input of the address memory, and a data input on said address memory connected to the output of the binary cyclical counter, the data output of said binary cyclical counter generating the storages addresses.

Claim 13

A system in accordance with any of the claims 5, further comprising an outgoing time multiplex line scanner, the field point memory having a data input connected to write enable selection wires of a storage address in the queueing file means, said selection wires being active during a first half byte duration, one bit write enable input being also connected to said selection wires and to the output of the outgoing time multiplex line scanner, a label translation memory, a first multiplexer, the scanner being enabled during the first bit period, the enabling being via first AND gates which individually pass the semantic priority bit coming from said label translation memory either at the output of the queueing file means being scanned or at an address input connected to the output of the first multiplexer, a binary cyclic counter, a second multiplexer, an address file, a first input of said first multiplexer being connected to the output of said binary cyclical counter and a second input of said first multiplexer being connected to the output of said second multiplexer, said second multiplexer having a first input which is connected to a data output of the queueing file means and having a second input connected to the output of the address file, the first multiplexer being controlled by said semantic priority bit and the second multiplexer being controlled during a second half byte period, and a data output connected to corresponding inputs of a NAND gate having an output connection to the write enable input of the address memory, and a data input on said address memory connected to the output of the binary cyclical counter, the data output of said binary cyclical counter generating the storages addresses.

Claim 14

A system in accordance with any of claims 6, further comprising an outgoing time multiplex line scanner, the field point memory having a data input connected to write enable selection wires of storage address in the queueing field means, said selection wires being active during a first half byte duration, one bit write enable input being also connected to said selection wires and to the output of the outgoing time multiplex line scanner, a label translation memory, a first multiplexer, the scanner being enabled during the first bit period, the enabling being via first AND gates which individually pass the semantic priority bit coming from said label translation memory either at the output of the queueing file means being scanned or at an address input connected to the output of the first multiplexer, a binary cyclic counter, a second multiplexer, an address file, a first input of said first multiplexer being connected to the output of said binary cyclical counter and a second input of said first multiplexer being connected to the output of said second multiplexer, said second multiplexer having a first input which is connected to a data output of the queueing file means and having a second input connected to the output of the address file, the first multiplexer being controlled by said semantic priority bit and the second multiplexer being controlled during a second half byte, and a data output connected to corresponding inputs of a NAND gate having an output connection to the write enable input of the address memory, and a data input on said address memory connected to the output of the binary cyclical counter, the data output of said binary cyclical counter generating the storages addresses.

Claim 15

A system in accordance with any of claims 7, further comprising an outgoing time multiplex line scanner, the field point memory having a data input connected to write enable selection wires of a storage address in the queueing file means, said selection wires being active during a first half byte duration, one bit write enable input being also connected to said selection wires and to the output of the outgoing time multiplex line scanner, a label translation memory, a first multiplexer, the scanner being enabled during the first bit period, the enabling being via first AND gates which individually pass the semantic priority bit coming from said label translation memory either at the output of the queueing file means being scanned or at an address input connected to the output of the first multiplexer, a binary cyclic counter, a second multiplexer, an address file, a first input of said first multiplexer being connected to the output of said binary cyclical counter and a second input of said first multiplexer being connected to the output of said second multiplexer, said second multiplexer having a first input which is connected to a data output of the queueing file means and having a second input connected to the output of the address file, the first multiplexer being controlled by said semantic priority bit and the second multiplexer being controlled during a second half byte period, and a data output connected to corresponding inputs of a NAND gate having an output connection to the write enable input of the address memory, and a data input on said address memory connected to the output of the binary cyclical counter, the data output of said binary cyclical counter generating the storages addresses.