Semiconductor integrated circuit including output buffer

Claim 2

A semiconductor integrated circuit having a test mode in addition to a normal mode, comprising: mode detecting means for detecting the test mode or normal mode and generating a mode signal corresponding to the detected mode; prebuffer means, having at least two selectable output driving capacities, for receiving the mode signal generated by said detecting means, the prebuffer means including means for amplifying an input signal in accordance with an output driving capacity corresponding to the mode signal, and for outputting the amplified signal; and output buffer means for receiving the amplified signal output from said prebuffer means and for outputting the amplified signal.

Claim 3

A circuit according to claim 1, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS inverter circuit for receiving a first input signal, and a second CMOS inverter circuit for receiving the first input signal, said second CMOS inverter circuit having an output terminal commonly connected to an output terminal of said first CMOS inverter circuit and being controlled in accordance with first and second mode signals, and a second prebuffer circuit including a third CMOS inverter circuit for receiving a second input signal, and a fourth CMOS inverter circuit for receiving the second input signal, said fourth CMOS inverter circuit having an output terminal commonly connected to an output terminal of said third CMOS inverter circuit and being controlled in accordance with the first and second mode signals; and said output buffer means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential, an output terminal for data, and the common output terminal of said first and second CMOS inverter circuits; and a second MOSFET of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential, said output terminal for data, and the common output terminal of said third and fourth CMOS inverter circuits.

Claim 4

A circuit according to claim 2, wherein each of said second and fourth CMOS inverter circuits comprises: an enhancement type first MOSFET of the first conductivity type having a source, a drain, and a gate, the source being connected to the first potential, and the first mode signal being supplied to the gate; an enhancement type second MOSFET of the first conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said first MOSFET and an output terminal, and the first or second input signal being supplied to the gate; an enhancement type third MOSFET of the second conductivity type having a source, a drain, and a gate, the source being connected to the second potential, and the second mode signal being supplied to the gate; and an enhancement type forth MOSFET of the second conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said third MOSFET and the output terminal, and the first or second mode signal being supplied to the gate.

Claim 5

A circuit according to claim 2, wherein each of said first and second CMOS inverter circuits comprises: a depletion type first MOSFET having a source, a drain, and a gate, the source being connected to the first potential, and the mode signal being supplied to the gate; an enhancement type second MOSFET of the first conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said first MOSFET and an output terminal, and the first or second input signal being supplied to the gate; a depletion type third MOSFET having a source, a drain, and a gate, the source being connected to the second potential, and the mode signal being supplied to the gate; and an enhancement type fourth MOSFET of the second conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said third MOSFET and the output terminal, and the first or second input signal being supplied to the gate.

Claim 6

A semiconductor integrated circuit having a test mode in addition to a normal mode, comprising: mode detecting means for detecting the test mode or normal mode and generating a mode signal corresponding to the detected mode; output buffer means whose driving capacity with respect to an external load is selectively set to one of at least two selectable output driving capacities to drive the external load by using a selected driving capacity, thereby outputting data; and prebuffer means for receiving the mode signal generated by said mode detecting means, for selecting a driving capacity of said output buffer means in accordance with the mode signal, the prebuffer means including means for amplifying an input signal in accordance with an output driving capacity of said output buffer means corresponding to the mode signal, and for supplying the amplified signal to said output buffer means.

Claim 7

A semiconductor integrated circuit having a test mode in addition to a normal mode, comprising: mode detecting means for detecting the test mode or normal mode and generating a mode signal corresponding to the detected mode; output buffer means whose driving capacity with respect to an external load is selectively set to one of at least two selectable output driving capacities to drive the external load by using a selected driving capacity, thereby outputting data; and prebuffer means for receiving the mode signal generated by said mode detecting means, for selecting a driving capacity of said output buffer means in accordance with the mode signal, the prebuffer means including means for amplifying an input signal in accordance with an output driving capacity of said output buffer means corresponding to the mode signal, and for supplying the amplified signal to said output buffer means.

Claim 8

A circuit according to claim 5, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS inverter circuit for receiving a first input signal, and a CMOS-NAND circuit for receiving the first input signal and a first mode signal, and a second prebuffer circuit including a second CMOS inverter circuit for receiving a second input signal, and a CMOS-NOR circuit for receiving the second input signal and a second mode signal; and said output buffer means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to the first potential, an output terminal for data, and an output terminal of said first CMOS inverter circuit, a second MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected the first potential, the output terminal for data, and an output terminal of said CMOS-NAND circuit, a third MOSFET of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential, the output terminal for data, and an output terminal of said second CMOS inverter circuit, and a fourth MOSFET of the second conductivity type having a source, a drain, and a gate respectively connected to the second potential, the output terminal for data, and an output terminal of said CMOS-NOR circuit.

Claim 9

A circuit according to claim 5, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS inverter circuit for receiving a first input signal, a second CMOS inverter circuit for receiving the first input signal, said second CMOS inverter circuit having an output terminal commonly connected to an output terminal of said first CMOS inverter circuit and being controlled in accordance with first and second mode signals, and a CMOS-NAND circuit for receiving the first input signal and the second mode signal, and a second prebuffer circuit including a third CMOS inverter circuit for receiving a second input signal, a fourth CMOS inverter circuit for receiving the second input signal, said fourth CMOS inverter circuit having an output terminal commonly connected to an output terminal of said third CMOS inverter circuit and being controlled in accordance with the first and second mode signals, and a CMOS-NOR circuit for receiving the second input signal and the first mode signal; and said output means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential, an output terminal for data, and the common output terminal of said first and second CMOS inverter circuits, a second MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected to the first potential, the output terminal for data, and an output terminal of said CMOS-NAND circuit, a third MOSFET of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential, the output terminal for data, and the common output terminal of said third and fourth CMOS inverter circuits, and a fourth MOSFET of the second conductivity type having a source, a drain, and a gate respectively connected to the second potential, the output terminal for data, and an output terminal of said CMOS-NOR circuit.

Claim 10

A semiconductor integrated circuit having a test mode in addition to a normal mode, comprising: mode detecting means for detecting the test mode or normal mode and generating a mode signal corresponding to the detected mode; output buffer means, having at least two selectable driving capacities, whose driving capacity with respect to an external load is selectively set to drive the external load by using a selected driving capacity, thereby outputting data; and prebuffer means for receiving the mode signal generated by said mode detecting means, for selecting a driving capacity of said output buffer means in accordance with the mode signal, the prebuffer means including means for amplifying an input signal, and for supplying the amplified signal to said output buffer means.

Claim 11

A semiconductor integrated circuit having a test mode in addition to a normal mode, comprising: mode detecting means for detecting the test mode or normal mode and generating a mode signal corresponding to the detected mode; output buffer means, having at least two selectable driving capacities, whose driving capacity with respect to an external load is selectively set to drive the external load by using a selected driving capacity, thereby outputting data; and prebuffer means for receiving the mode signal generated by said mode detecting means, for selecting a driving capacity of said output buffer means in accordance with the mode signal, the prebuffer means including means for amplifying an input signal, and for supplying the amplified signal to said output buffer means.

Claim 12

A circuit according to claim 8, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS-NAND circuit for receiving a first input signal and a first mode signal, and a second CMOS-NAND circuit for receiving the first input signal and a second mode signal, and a second prebuffer circuit including a first CMOS-NOR circuit for receiving a second input signal and the second mode signal, and a second CMOS-NOR circuit for receiving the second input signal and the first mode signal; and said output buffer means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to the first potential, an output terminal for data, and an output terminal of said first CMOS-NAND circuit, a second MOSFET of the first conductivity type having a source, a drain and a gate respectively connected the first potential, the output terminal for data, and an output terminal of said second CMOS-NAND circuit, a third MOSFET of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential, the output terminal for data, and an output terminal of said first CMOS-NOR circuit, and a fourth MOSFET of the second conductivity type having a source, a drain, and a gate respectively connected to the second potential, the output terminal for data, and an output terminal of said second CMOS-NOR circuit.

Claim 13

A circuit according to claim 8, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS-NOR circuit for receiving a first input signal and a first mode signal, and a second CMOS-NOR circuit for receiving the first input signal and a second mode signal, and a second prebuffer circuit including a third CMOS-NOR circuit for receiving a second input signal and the first mode signal, and a fourth CMOS-NOR circuit for receiving the second input signal and the second mode signal; and said output buffer means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential, an output terminal for data, and an output terminal of said first CMOS-NOR circuit, a second MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected to the first potential, the output terminal for data, and an output terminal of said second CMOS-NOR circuit, a third MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected to a second potential, the output terminal for data, and an output terminal of said third CMOS-NOR circuit, and a fourth MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected to the second potential, the output terminal for data, and an output terminal of said fourth CMOS-NOR circuit.

Claim 14

A semiconductor integrated circuit comprising: a programmable nonvolatile memory circuit having a normal data read mode and a programming mode accompanied by a verify operation; mode detecting means for detecting an operation mode of said nonvolatile memory circuit and generating a mode signal corresponding to the detected mode; prebuffer means, having at least two selectable output driving capacities, for receiving the mode signal generated by said mode detecting means, the prebuffer means including means for amplifying data read out from said nonvolatile memory circuit in accordance with an output driving capacity corresonding to the mode signal, and for outputting the amplified data; and output buffer means for receiving the amplified data output from said prebuffer means, and for externally outputting the data read out from asid nonvolatile memory circuit.

Claim 15

A semiconductor integrated circuit comprising: a programmable nonvolatile memory circuit having a normal data read mode and a programming mode accompanied by a verify operation; mode detecting means for detecting an operation mode of said nonvolatile memory circuit and generating a mode signal corresponding to the detected mode; prebuffer means, having at least two selectable output driving capacities, for receiving the mode signal generated by said mode detecting means, the prebuffer means including means for amplifying data read out from said nonvolatile memory circuit in accordance with an output driving capacity corresonding to the mode signal, and for outputting the amplified data; and output buffer means for receiving the amplified data output from said prebuffer means, and for externally outputting the data read out from asid nonvolatile memory circuit.

Claim 16

A circuit according to claim 11, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS inverter circuit for receiving a first input signal, and a second CMOS inverter circuit for receiving the first input signal, said second CMOS inverter circuit having an output terminal commonly connected to an output terminal of said first CMOS inverter circuit and being controlled in accordance with first and second mode signals, and a second prebuffer circuit including a third CMOS inverter circuit for receiving a second input signal, and a fourth CMOS inverter circuit for receiving the second input signal, said fourth CMOS inverter circuit having an output terminal commonly connected to an output terminal of said third CMOS inverter circuit and being controlled in accordance with the first and second mode signals; and said output buffer means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential, an output terminal for data, and the common output terminal of said first and second CMOS inverter circuits; and a second MOSFET of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential, said output terminal for data, and the common output terminal of said third and fourth CMOS inverter circuits.

Claim 17

A circuit according to claim 12, wherein each of said second and fourth CMOS inverter circuits comprises: an enhancement type first MOSFET of the first conductivity type having a source, a drain, and a gate, the source being connected to the first potential, and the first mode signal being supplied to the gate; an enhancement type second MOSFET of the first conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said first MOSFET and an output terminal, and the first or second input signal being supplied to the gate; an enhancement type third MOSFET of the second conductivity type having a source, a drain, and a gate, the source being connected to the second potential, and the second mode signal being supplied to the gate; and an enhancement type forth MOSFET of the second conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said third MOSFET and the output terminal, and the first or second mode signal being supplied to the gate.

Claim 18

A circuit according to claim 12, wherein each of said first and second CMOS inverter circuits comprises: a depletion type first MOSFET having a source, a drain, and a gate, the source being connected to the first potential, and the mode signal being supplied to the gate; an enhancement type second MOSFET of the first conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said first MOSFET and an output terminal, and the first or second input signal being supplied to the gate; a depletion type third MOSFET having a source, a drain, and a gate, the source being connected to the second potential, and the mode signal being supplied to the gate; and an enhancement type fourth MOSFET of the second conductivity type having a source, a drain, and a gate, the source and the drain being respectively connected to the drain of said third MOSFET and the output terminal, and the first or second input signal being supplied to the gate.

Claim 19

A semiconductor integrated circuit comprising: a programmable nonvolatile memory circuit having a normal data read mode and a programming mode accompanied by a verify operation; mode detecting means for detecting an operation mode of said nonvolatile memory circuit and generating a mode signal corresponding to the detected mode; output buffer means, having a plurality of types of driving capacities to be selectively set with respect to an external load, for driving the external load by using a selected driving capacity and for outputting data read out from said nonvolatile memory circuit; and prebuffer means for receiving the mode signal generated by said mode detecting means and for selecting a driving capacity of said output buffer means in accordance with the mode signal, the prebuffer means including means for amplifying the data read out from said nonvolatile memory circuit in accordance with the driving capacity corresponding to the mode signal, and supplying the amplified output to said data buffer means.

Claim 20

A semiconductor integrated circuit comprising: a programmable nonvolatile memory circuit having a normal data read mode and a programming mode accompanied by a verify operation; mode detecting means for detecting an operation mode of said nonvolatile memory circuit and generating a mode signal corresponding to the detected mode; output buffer means, having a plurality of types of driving capacities to be selectively set with respect to an external load, for driving the external load by using a selected driving capacity and for outputting data read out from said nonvolatile memory circuit; and prebuffer means for receiving the mode signal generated by said mode detecting means and for selecting a driving capacity of said output buffer means in accordance with the mode signal, the prebuffer means including means for amplifying the data read out from said nonvolatile memory circuit in accordance with the driving capacity corresponding to the mode signal, and supplying the amplified output to said data buffer means.

Claim 21

A circuit according to claim 15, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS inverter circuit for receiving a first input signal, and a CMOS-NAND circuit for receiving the first input signal and a first mode signal, and a second prebuffer circuit including a second CMOS inverter circuit for receiving a second input signal, and a CMOS-NOR circuit for receiving the second input signal and a second mode signal; and said output buffer means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to the first potential, an output terminal for data, and an output terminal of said first CMOS inverter circuit, a second MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected the first potential, the output terminal for data, and an output terminal of said CMOS-NAND circuit, a third MOSFET of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential, the output terminal for data, and an output terminal of said second CMOS inverter circuit, and a fourth MOSFET of the second conductivity type having a source, a drain, and a gate respectively connected to the second potential, the output terminal for data, and an output terminal of said CMOS-NOR circuit.

Claim 22

A circuit according to claim 15, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS inverter circuit for receiving a first input signal, a second CMOS inverter circuit for receiving the first input signal, said second CMOS inverter circuit having an output terminal commonly connected to an output terminal of said first CMOS inverter circuit and being controlled in accordance with first and second mode signals, and a CMOS-NAND circuit for receiving the first input signal and the second mode signal, and a second prebuffer circuit including a third CMOS inverter circuit for receiving a second input signal, a fourth CMOS inverter circuit for receiving the second input signal, said fourth CMOS inverter circuit having an output terminal commonly connected to an output terminal of said third CMOS inverter circuit and being controlled in accordance with the first and second mode signals, and a CMOS-NOR circuit for receiving the second input signal and the first mode signal; and said output means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential, an output terminal for data, and the common output terminal of said first and second CMOS inverter circuits, a second MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected to the first potential, the output terminal for data, and an output terminal of said CMOS-NAND circuit, a third MOSFET of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential, the output terminal for data, and the common output terminal of said third and fourth CMOS inverter circuits, and a fourth MOSFET of the second conductivity type having a source, a drain, and a gate respectively connected to the second potential, the output terminal for data, and an output terminal of said CMOS-NOR circuit.

Claim 23

A semiconductor integrated circuit comprising: a programmable nonvolatile memory circuit having a normal data read mode and a programming mode accmopanied by a verify operation; mode detecting means for detecting an operation mode of said nonvolatile memory circuit and generating a mode signal corresponding to the detected mode; output buffer means, having a plurality of types of driving capacities to be selectively set with respect to an external load, for driving the external load in accordance with a selected driving capacity and for ouputting data read out from said nonvolatile memory circuit; and prebuffer means for receiving the mode signal generated by said mode detecting means and for selecting a driving capacity of said output buffer means in accordance with the mode signal, the prebuffer means including means for amplifying the data read out from said nonvolatile memory circuit, and for supplying the amplified data to said output buffer means.

Claim 24

A semiconductor integrated circuit comprising: a programmable nonvolatile memory circuit having a normal data read mode and a programming mode accmopanied by a verify operation; mode detecting means for detecting an operation mode of said nonvolatile memory circuit and generating a mode signal corresponding to the detected mode; output buffer means, having a plurality of types of driving capacities to be selectively set with respect to an external load, for driving the external load in accordance with a selected driving capacity and for ouputting data read out from said nonvolatile memory circuit; and prebuffer means for receiving the mode signal generated by said mode detecting means and for selecting a driving capacity of said output buffer means in accordance with the mode signal, the prebuffer means including means for amplifying the data read out from said nonvolatile memory circuit, and for supplying the amplified data to said output buffer means.

Claim 25

A circuit according to claim 18, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS-NAND circuit for receiving a first input signal and a first mode signal, and a second CMOS-NAND circuit for receiving the first input signal and a second mode signal, and a second prebuffer circuit including a first CMOS-NOR circuit for receiving a second input signal and the second mode signal, and a second CMOS-NOR circuit for receiving the second input signal and the first mode signal; and said output buffer means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to the first potential, an output terminal for data, and an output terminal of said first CMOS-NAND circuit, a second MOSFET of the first conductivity type having a source, a drain and a gate respectively connected the first potential, the output terminal for data, and an output terminal of said second CMOS-NAND circuit, a third MOSFET of a second conductivity type having a source, a drain, and a gate respectively connected to a second potential, the output terminal for data, and an output terminal of said first CMOS-NOR circuit, and a fourth MOSFET of the second conductivity type having a source, a drain, and a gate respectively connected to the second potential, the output terminal for data, and an output terminal of said second CMOS-NOR circuit.

Claim 26

A circuit according to claim 18, wherein said prebuffer means comprises: a first prebuffer circuit including a first CMOS-NOR circuit for receiving a first input signal and a first mode signal, and a second CMOS-NOR circuit for receiving the first input signal and a second mode signal, and a second prebuffer circuit including a third CMOS-NOR circuit for receiving a second input signal and the first mode signal, and a fourth CMOS-NOR circuit for receiving the second input signal and the second mode signal; and said output buffer means comprises: a first MOSFET of a first conductivity type having a source, a drain, and a gate respectively connected to a first potential, an output terminal for data, and an output terminal of said first CMOS-NOR circuit, a second MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected to the first potential, the output terminal for data, and an output terminal of said second CMOS-NOR circuit, a third MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected to a second potential, the output terminal for data, and an output terminal of said third CMOS-NOR circuit, and a fourth MOSFET of the first conductivity type having a source, a drain, and a gate respectively connected to the second potential, the output terminal for data, and an output terminal of said fourth CMOS-NOR circuit.