Patent US5045951A successfully refreshed from Google Patents.
US5045951A
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Video signal processor and video signal processing method for a video printer
Assignee: Hitachi Ltd
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Filing: 1989-08-31
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Granted: 1991-09-03
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Expires: 2009-08-31
Abstract
Abstract A video signal processing circuit for a video printer operating to sample an analog video signal, to convert the video signal into digital data, to store the data in a memory, and to read out the contents of memory to a printer for printing. The circuit includes an oscillation circuit which generates a pixel clock in response to the horizontal sync signal in the video signal, a frequency division phase shift circuit which divides the frequency of the pixel clock provided by the oscillation circuit and shifts the frequency divided clock with the pixel clock, a selection circuit which selects one of frequency divided clocks having different phases provided by the frequency division phase shift circuit, and a selection control circuit which operates on the selection circuit to alter the clock selection at each arrival of vertical sync signal, so that the sampling of the video signal is implemented in response to the clock output of the selection control circuit.
Inventors
- 👤 Hiroyuki Kimura
- 👤 Kentaro Hamma
- 👤 Yasunori Kobori
- 👤 Takashi Omata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:54
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/00127; H04N1/00281; H04N1/00283; H04N1/00291; H04N1/00294; H04N1/40; H04N1/46; H04N1/64; H04N1/646; H04N1/648
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
236 words
A video signal process controller for a video printer having sampling means for sampling a video signal, analog-to-digital conversion means for converting the sampled video signal into a digital signal, memory means for storing the converted digital signal, and printer means for reading out contents of said memory means and for recording the contents on a recording medium, said controller comprising: extraction means for extracting a horizontal sync signal and a vertical sync signal from the video signal; oscillation means for oscillating in synchronism with the extracted horizontal sync signal in order to generate a pixel clock signal having a pixel clock signal frequency; frequency division means for dividing the frequency of the pixel clock signal generated by the oscillation means to produce a frequency divided clock signal; phase shift means which produces, by shifting the frequency divided clock signal in accordance with the pixel clock signal, multiple types of frequency divided clock signals out of phase from each other by 1-pixel clock signal period; selection means for selecting one of the multiple types of frequency divided clock signals from said phase shift means as a sampling pulse signal in response to which the video signal is sampled by the sampling means; and selection control means for operating on said selection means in order to sequentially select a different type of frequency divided clock signal in response to the vertical sync signal from said extraction means.
Claim 2
Dependent Claim
236 words
A video signal process controller for a video printer having sampling means for sampling a video signal, analog-to-digital conversion means for converting the sampled video signal into a digital signal, memory means for storing the converted digital signal, and printer means for reading out contents of said memory means and for recording the contents on a recording medium, said controller comprising: extraction means for extracting a horizontal sync signal and a vertical sync signal from the video signal; oscillation means for oscillating in synchronism with the extracted horizontal sync signal in order to generate a pixel clock signal having a pixel clock signal frequency; frequency division means for dividing the frequency of the pixel clock signal generated by the oscillation means to produce a frequency divided clock signal; phase shift means which produces, by shifting the frequency divided clock signal in accordance with the pixel clock signal, multiple types of frequency divided clock signals out of phase from each other by 1-pixel clock signal period; selection means for selecting one of the multiple types of frequency divided clock signals from said phase shift means as a sampling pulse signal in response to which the video signal is sampled by the sampling means; and selection control means for operating on said selection means in order to sequentially select a different type of frequency divided clock signal in response to the vertical sync signal from said extraction means.
Claim 3
Dependent Claim
88 words
A video signal process controller according to claim 1, wherein said frequency division means divides the pixel clock signal frequency by 1/N, where N is an integer greater than one, said phase shift means generates N kinds of frequency divided clock signals, and said selection control means operates on said selection means to sequentially select one of N types of frequency divided clock signals in response to the vertical sync signal, so that pixel data for one picture in the video signal is sampled by the sampling means.
Claim 4
Dependent Claim
178 words
A video signal process controller according to claim 1 or 2, wherein said memory means comprises a first memory which receives the converted digital signal to store pixel data of the video signal for the one picture, and a second memory which stores the digital signal for a portion of the picture read out of said first memory, and wherein said video signal process controller further comprises: write address generation means which generates a write address for storing the digital signal from said conversion means into said first memory in response to the sampling pulse signal from the selection means and delivers the write address to said first memory; means for generating a read clock signal; and read address generation means which generates a read address for reading out the digital signal from said first memory and delivers the read address to said second memory, said printer means reading out the digital signal from said second memory each time the digital signal has been stored in said second memory and recording the digital signal on the recording medium.
Claim 5
Dependent Claim
54 words
A video signal process controller according to claim 3, wherein said write address generation means generates, as the write address, stepping addresses at an N address interval in response to the sampling pulse signal, and said read address generation means generates, as the read address, continuous addresses in response to a read clock signal.
Claim 6
Dependent Claim
54 words
A video signal process controller according to claim 3, wherein said write address generation means generates, as the write address, continuous addresses in response to the sampling pulse signal, and said read address generation means generates, as the read address, stepping addresses at an N address interval in response to a read clock signal.
Claim 7
Dependent Claim
48 words
A video signal process controller according to claim 3, further comprising counting means for counting the vertical sync signal and means for halting the generation of the write address by said write address generation means when a count value of said counting means reaches a count of N+1.
Claim 8
Dependent Claim
122 words
A video signal processing controller according to claim 1, wherein said memory means receives the converted digital signal in order to store a portion of a picture in the video signal, and wherein said video signal process controller further comprises gate means which selectively passes one of multiple sampling pulses selected by said selection means to the sampling means, and means for controlling said gate means in order to sequentially switch the selection of a sampling pulse by said selection means in response to the vertical sync signal, and wherein the digital signal from said memory means is read out and recorded on the recording medium by the printer means each time the digital signal has been stored in said memory means.
Claim 9
Dependent Claim
56 words
A video signal process controller according to claim 1, further comprising first signal generation means for generating a first signal indicative of a recording segment of the video signal and gate means for passing the sampling pulse signal from said selection means to the sampling means only for the recording segment indicated by the first signal.
Claim 10
Dependent Claim
25 words
A video signal process controller according to claim 8, wherein said first signal indicates a recording segment of the video signal within a horizontal period.
Claim 11
Dependent Claim
44 words
A video signal process controller according to claim 9, further comprising means for controlling said first signal generation means so that the first signal is shifted in phase by 1-pixel clock period sequentially in response to each of a plurality of vertical sync signals.
Claim 12
Dependent Claim
36 words
A video signal process controller according to claim, 9 further comprising means of for controlling said first signal generation means so that the first signal is controlled in phase in accordance with an intended recording segment.
Claim 13
Dependent Claim
25 words
A video signal process controller according to claim 8, wherein the first signal indicates a recording segment of the video signal within a vertical period.
Claim 14
Dependent Claim
87 words
A video signal process controller according to claim 1, further comprising: first signal generation means for generating a first signal indicative of a recording segment of the video signal within a horizontal period; second signal generation means for generating a second signal indicative of a recording segment of the video signal within a vertical period; and gate means for passing the sampling pulse signal from said selection means to the sampling means only for a segment in which segments indicated by said first and second signals overlap.
Claim 15
Dependent Claim
202 words
A video signal process control method for a video printer having sampling means for sampling a video signal, analog-to-digital conversion means for converting the sampled video signal into a digital signal, memory means for storing the converted digital signal, and printer means for reading out contents of said memory and for recording the contents on a recording medium, said method comprising the steps of: extracting a horizontal sync signal and a vertical sync signal from the video signal; oscillating in synchronism with the extracted horizontal sync signal in order to generate a pixel clock signal having a pixel clock signal frequency; dividing the frequency of the pixel clock signal in order to produce a frequency divided clock signal; producing, by shifting the frequency divided clock signal in accordance with the pixel clock signal, multiple types of frequency divided clock signals out of phase from each other by 1-pixel clock signal period; selecting one of the multiple types of frequency divided clock signals sequentially as a sampling pulse signal; and sequentially selecting a different type of frequency divided clock signal in response to the vertical sync signal, the video signal being sampled by said sampling means in response to the sampling pulse signal.
Claim 16
Dependent Claim
202 words
A video signal process control method for a video printer having sampling means for sampling a video signal, analog-to-digital conversion means for converting the sampled video signal into a digital signal, memory means for storing the converted digital signal, and printer means for reading out contents of said memory and for recording the contents on a recording medium, said method comprising the steps of: extracting a horizontal sync signal and a vertical sync signal from the video signal; oscillating in synchronism with the extracted horizontal sync signal in order to generate a pixel clock signal having a pixel clock signal frequency; dividing the frequency of the pixel clock signal in order to produce a frequency divided clock signal; producing, by shifting the frequency divided clock signal in accordance with the pixel clock signal, multiple types of frequency divided clock signals out of phase from each other by 1-pixel clock signal period; selecting one of the multiple types of frequency divided clock signals sequentially as a sampling pulse signal; and sequentially selecting a different type of frequency divided clock signal in response to the vertical sync signal, the video signal being sampled by said sampling means in response to the sampling pulse signal.
Claim 17
Dependent Claim
52 words
A video signal process control method according to claim 14, wherein the frequency divided clock signal is produced by dividing the pixel clock signal frequency by 1/N, where N is an integer greater than 1, and said multiple types of frequency divided clock signals include four types of frequency divided clock signals.
Claim 18
Dependent Claim
164 words
A video signal process control method according to claim 14 or 15, wherein said memory means comprises a first memory which receives the converted digital signal in order to store pixel data of the video signal for one picture, and a second memory which stores the digital signal for a portion of the picture read out of said first memory, and wherein said video signal process control method further comprises the steps of: generating a write address for storing the digital signal from said conversion means into said first memory in response to the sampling pulse signal and delivering the write address to said first memory; and generating a read address for reading out the digital signal from said first memory and delivering the read address to said second memory; wherein said printer means reads out the digital signal from said second memory each time the digital signal has been stored in said second memory and records the digital signal on the recording medium.
Claim 19
Dependent Claim
130 words
A video signal process control method according to claim 14, wherein said memory means receives the converted digital signal in order to store part of a picture in the video signal, and wherein the video signal process control method further comprises the steps of: selectively passing one of multiple sampling pulse output from selection means for selecting one of the multiple types of frequency divided clock signals as the sampling pulse signal to said sampling means; and controlling a gate to sequentially switch selection of a sampling pulse signal in response to the vertical sync signal; wherein said printer means reads out the digital signal from said memory means and records the digital signal on the recording medium each time the digital signal has been stored in said memory means.
Claim 20
Dependent Claim
67 words
A video signal process control method according to claim 14, further comprising the steps of: generating a first signal indicative of a recording segment of the video signal; and passing the sampling pulse signal from selection means for selecting one of the multiple types of frequency divided clock signals as the sampling pulse signal to said sampling means only for the segment indicated by the first signal.
Claim 21
Dependent Claim
74 words
A video signal process control method according to claim 14, further comprising the steps of: generating a first signal indicative of a recording segment of the video signal within a horizontal period; generating a second signal indicative of a recording segment of the video signal within a vertical period; and passing the sampling pulse signal to said sampling means only for a segment in which segments indicated by said first and second signals overlap.
Claim 22
Dependent Claim
233 words
A video printer comprising: sampling means for sampling a video signal in response to a sampling pulse signal; analog-to-digital conversion means for converting the sampled video signal into a digital signal; memory means for storing the converted digital signal; printer means for reading out contents of said memory means and for recording the contents on a recording medium; extraction means for extracting a horizontal sync signal and a vertical sync signal from the video signal; oscillation means for oscillating in synchronism with the extracted horizontal sync signal in order to generate a pixel clock signal having a pixel clock signal frequency; frequency division means for dividing the frequency of the pixel clock signal generated by the oscillation means to produce a frequency divided clock signal; phase shift means which produces, by shifting the frequency divided clock signal in accordance with the pixel clock signal, multiple types of frequency divided clock signals out of phase from each other by 1-pixel clock signal period; selection means for selecting one of the multiple types of frequency divided clock signals from said phase shift means as the sampling pulse signal in response to which the video signal is sampled by the sampling means; and selection control means for operating on said selection means in order to sequentially select a different type of frequency divided clock signal in response to the vertical sync signal from said extraction means.
Claim 23
Dependent Claim
233 words
A video printer comprising: sampling means for sampling a video signal in response to a sampling pulse signal; analog-to-digital conversion means for converting the sampled video signal into a digital signal; memory means for storing the converted digital signal; printer means for reading out contents of said memory means and for recording the contents on a recording medium; extraction means for extracting a horizontal sync signal and a vertical sync signal from the video signal; oscillation means for oscillating in synchronism with the extracted horizontal sync signal in order to generate a pixel clock signal having a pixel clock signal frequency; frequency division means for dividing the frequency of the pixel clock signal generated by the oscillation means to produce a frequency divided clock signal; phase shift means which produces, by shifting the frequency divided clock signal in accordance with the pixel clock signal, multiple types of frequency divided clock signals out of phase from each other by 1-pixel clock signal period; selection means for selecting one of the multiple types of frequency divided clock signals from said phase shift means as the sampling pulse signal in response to which the video signal is sampled by the sampling means; and selection control means for operating on said selection means in order to sequentially select a different type of frequency divided clock signal in response to the vertical sync signal from said extraction means.
Claim 24
Dependent Claim
86 words
A video printer according to claim 20, wherein said frequency division means divides the pixel clock signal frequency by 1/N, where N is an integer greater than one, said phase shift means generates N kinds of frequency divided clock signals, and said selection control means operates on said selection means to sequentially select one of N types of frequency divided clock signals in response to the vertical sync signal, so that pixel data for one picture in the video signal is sampled by the sampling means.
Claim 25
Dependent Claim
174 words
A video printer according to claim 21, wherein said memory means comprises a first memory which receives the converted digital signal to store pixel data of the video signal for the one picture, and a second memory which stores the digital signal for a portion of the picture read out of said first memory, and wherein said video signal process controller further comprises: write address generation means which generates a write address for storing the digital signal from said conversion means into said first memory in response to the sampling pulse signal from the selection means and delivers the write address to said first memory; means for generating a read clock signal; and read address generation means which generates a read address for reading out the digital signal from said first memory and delivers the read address to said second memory, said printer means reading out the digital signal from said second memory each time the digital signal has been stored in said second memory and recording the digital signal on the recording medium.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |