TTL/ECL translator circuit

Claim 2

A circuit for translating TTL level input signals, which have a high voltage state and a low voltage state, to ECL level output signals, which have a high voltage state and a low voltage state, the circuit comprising: (a) first and second voltage nodes; (b) TTL input means, coupled to the first voltage node, for receiving the TTL level input signals and for generating a first intermediate voltage at the first voltage node corresponding to the TTL level input signals; (c) a level shifter, coupled to the first and second voltage nodes, responsive to the first intermediate voltage, for generating a second intermediate voltage at the second voltage node corresponding to the first intermediate voltage; and (d) ECL output means, coupled to the second voltage node, responsive to the second intermediate voltage, for generating ECL level output signals corresponding to the second intermediate voltage, thereby providing ECL level output signals corresponding to TTL level input signals.

Claim 3

The circuit of claim 1 wherein the TTL input means comprises: (a) a TTL input buffer, coupled to the first voltage node, for receiving the TTL level input signals and for generating a first intermediate voltage at the first voltage node corresponding to the TTL level input signals; and (b) an input clamp, coupled to the TTL input buffer, for preventing the TTL level input signals from causing voltage ringing in the TTL input buffer.

Claim 4

The circuit of claim 2 wherein the TTL input buffer includes a TTL input threshold means for providing a threshold voltage level between a TTL high voltage level and a TTL low voltage level.

Claim 5

The circuit of claim 1 wherein the level shifter comprises: (a) an intermediate translation means, coupled to the first and second voltage nodes, responsive to the first intermediate voltage, for generating a second intermediate voltage at the second voltage node corresponding to the first intermediate voltage; and (b) an ECL current source, coupled to the intermediate translation means, for providing current to the intermediate translation means.

Claim 6

The circuit of claim 4 wherein the intermediate translation means includes a translation diode.

Claim 7

The circuit of claim 5 wherein the translation diode comprises a transistor connected as a diode.

Claim 8

The circuit of claim 4 wherein the level shifter further comprises a preliminary voltage shifter coupled to the first voltage node and the intermediate translation means for decreasing the voltage signal provided to the intermediate translation means.

Claim 9

The circuit of claim 7 wherein the preliminary voltage shifter means comprises a resistor and a diode.

Claim 10

The circuit of claim 1 wherein the ECL output means comprises: (a) an ECL output driver, coupled to the second voltage node, responsive to the second intermediate voltage, for generating ECL level output signals at the ECL output node corresponding to the second intermediate voltage; and (b) a low level clamp, coupled to the second voltage node, for preventing the ECL output driver from generating a continuous low voltage ECL output signal.

Claim 11

The circuit of claim 9 wherein the low level clamp comprises a diode.

Claim 12

The circuit of claim 10 wherein the diode comprises a transistor connected as a diode.

Claim 13

A circuit for translating TTL level input signals, which have a high voltage state and a low voltage state, to ECL level output signals, which have a high voltage state and a low voltage state, the circuit comprising: (a) first and second voltage nodes; (b) a TTL input buffer, coupled to the first voltage node, for receiving the TTL level input signals and for generating a first intermediate voltage at the first voltage node corresponding to the TTL level input signals; (c) a translation means, coupled to the first and second voltage nodes, responsive to the first intermediate voltage, for generating a second intermediate voltage at the second voltage node corresponding to the first intermediate voltage; (d) an ECL current source, coupled to the translation means, for providing current to the translation means; (e) an ECL output driver, coupled to the second voltage node, responsive to the second intermediate voltage, for generating ECL level output signals at the ECL output node corresponding to the second intermediate voltage; and (f) a low level clamp, coupled to the second voltage node and the ECL output driver, for preventing the ECL output driver from generating a continuous low voltage ECL output signal.

Claim 14

A circuit for translating TTL level input signals, which have a high voltage state and a low voltage state, to ECL level output signals, which have a high voltage state and a low voltage state, the circuit comprising: (a) first and second voltage nodes; (b) a TTL input buffer, coupled to the first voltage node, for receiving the TTL level input signals and for generating a first intermediate voltage at the first voltage node corresponding to the TTL level input signals; (c) a translation means, coupled to the first and second voltage nodes, responsive to the first intermediate voltage, for generating a second intermediate voltage at the second voltage node corresponding to the first intermediate voltage; (d) an ECL current source, coupled to the translation means, for providing current to the translation means; (e) an ECL output driver, coupled to the second voltage node, responsive to the second intermediate voltage, for generating ECL level output signals at the ECL output node corresponding to the second intermediate voltage; and (f) a low level clamp, coupled to the second voltage node and the ECL output driver, for preventing the ECL output driver from generating a continuous low voltage ECL output signal.

Claim 15

The circuit of claim 12 further comprising a preliminary voltage shifter coupled to the first voltage node and the translation means for decreasing the voltage signal provided to the translation means.