Flash EEPROM memory systems having multistate storage cells

Claim 2

A split-channel EEPROM device formed on a semiconductor substrate surface and having more than two distinct memory states, comprising: source and drain regions formed in said substrate surface and separated by a channel region divided into first and second adjacent portions, a control gate positioned adjacent said source region and extending across the first portion of said channel region with a first gate dielectric layer therebetween in a manner to control conduction through the first channel portion in accordance with a level of voltage applied to the control gate, thereby forming a first transistor having a fixed threshold voltage, a floating gate positioned adjacent said drain region and extending across the second portion of said channel region with a second gate dielectric layer therebetween in a manner to control conduction through the second channel portion in accordance with a level of electron charge stored thereon, said control gate also extending over at least a portion of the floating gate and being insulated therefrom, thereby forming a second transistor having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, an erase gate positioned adjacent the floating gate with a tunnel dielectric layer therebetween, and means operably connected with at least said source, said drain, said control gate and said erase gate for programming and reading any one of more than two programmable threshold states of said second transistor that results from any respective one of more than two levels of net charge being placed onto the floating gate, said second transistor given threshold level being at least three volts, and wherein a majority of said more than two programmable threshold states result from a net positive charge on the floating gate, whereby long-term charge retention is improved for storing more than two memory states.

Claim 3

A split-channel EEPROM device formed on a semiconductor substrate surface and having more than two distinct memory states, comprising: source and drain regions formed in said substrate surface and separated by a channel region divided into first and second adjacent portions, a control gate positioned adjacent said source region and extending across the first portion of said channel region with a first gate dielectric layer therebetween in a manner to control conduction through the first channel portion in accordance with a level of voltage applied to the control gate, thereby forming a first transistor having a fixed threshold voltage, a floating gate positioned adjacent said drain region and extending across the second portion of said channel region with a second gate dielectric layer therebetween in a manner to control conduction through the second channel portion in accordance with a level of electron charge stored thereon, said control gate also extending over at least a portion of the floating gate and being insulated therefrom, thereby forming a second transistor having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, said second transistor given threshold level being at least three volts and greater than the fixed threshold of said first transistor, an erase gate positioned adjacent the floating gate with a tunnel dielectric layer therebetween, and means operably connected with at least said source, said drain, said control gate and said erase gate for programming and reading any one of more than two programmable threshold states of said second transistor that results from any respective one of more than two levels of net charge being placed onto the floating gate, a majority of said more than two programmable threshold states resulting from a net positive charge on the floating gate, whereby long-term charge retention is improved for storing more than two memory states.

Claim 4

A split-channel EEPROM device formed on a semiconductor substrate surface and having more than two distinct memory states, comprising: source and drain regions formed in said substrate surface and separated by a channel region divided into first and second adjacent portions, a control gate positioned adjacent said source region and extending across the first portion of said channel region with a first gate dielectric layer therebetween in a manner to control conduction through the first channel portion in accordance with a level of voltage applied to the control gate, thereby forming a first transistor having a fixed threshold voltage, a floating gate positioned adjacent said drain region and extending across the second portion of said channel region with a second gate dielectric layer therebetween in a manner to control conduction through the second channel portion in accordance with a level of electron charge stored thereon, said control gate also extending over at least a portion of the floating gate and being insulated therefrom, thereby forming a second transistor having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, said second transistor given threshold level being at least three volts and greater than the fixed threshold of said first transistor, an erase gate positioned adjacent the floating gate with a tunnel dielectric layer therebetween, and means operably connected with at least said source, said drain, said control gate and said erase gate for programming and reading any one of more than two programmable threshold states of said second transistor that results from any respective one of more than two levels of net charge being placed onto the floating gate, a majority of said more than two programmable threshold states resulting from a net positive charge on the floating gate, whereby long-term charge retention is improved for storing more than two memory states.

Claim 5

The device according to any one of claim 1 or 2 wherein said second transistor given threshold level is established sufficiently high in order that all of said programmable threshold states result from a net positive charge on the floating gate.

Claim 11

An EEPROM device, comprising: source and drain regions formed in a semiconductor substrate surface and separated across said surface by a channel region, a control gate extending across the channel region between the source and drain regions and separated from the substrate surface by a gate dielectric layer across a first portion of the channel, thereby formed a first transistor structure having a fixed threshold voltage level, a floating gate positioned between the control gate and the substrate surface across a second portion of the channel adjacent said first channel portion, said floating gate being separated from the substrate surface in the second channel portion by a gate dielectric layer and from said control gate by another dielectric layer, thereby forming a second transistor structure in series with said first transistor structure and having a variable threshold level determined by a net effect of a given threshold level corresponding to a neutral charge on the floating gate and an amount of electron charge stored on the floating gate, an erase gate positioned adjacent the floating gate with a tunnel dielectric layer therebetween, means electrically connected with at least the source, drain, control gate and erase gate for storing any one of more than two different predetermined levels of electron charge on the floating gate, at least a majority of which are net positive charge levels on the floating gate, means electrically connected with at least said source, drain and control gate for reading a level of current between said source and drain that is proportional to the level of charge stored on the floating gate, and said second transistor having its said given threshold level set at at least three volts and that is said at least a majority of floating gate charge levels are separated such that corresponding levels of current between the source and drain are separately detectable by said reading means.

Claim 12

An EEPROM device, comprising: source and drain regions formed in a semiconductor substrate surface and separated across said surface by a channel region, a control gate extending across the channel region between the source and drain regions and separated from the substrate surface by a gate dielectric layer across a first portion of the channel, thereby formed a first transistor structure having a fixed threshold voltage level, a floating gate positioned between the control gate and the substrate surface across a second portion of the channel adjacent said first channel portion, said floating gate being separated from the substrate surface in the second channel portion by a gate dielectric layer and from said control gate by another dielectric layer, thereby forming a second transistor structure in series with said first transistor structure and having a variable threshold level determined by a net effect of a given threshold level corresponding to a neutral charge on the floating gate and an amount of electron charge stored on the floating gate, an erase gate positioned adjacent the floating gate with a tunnel dielectric layer therebetween, means electrically connected with at least the source, drain, control gate and erase gate for storing any one of more than two different predetermined levels of electron charge on the floating gate, at least a majority of which are net positive charge levels on the floating gate, means electrically connected with at least said source, drain and control gate for reading a level of current between said source and drain that is proportional to the level of charge stored on the floating gate, and said second transistor having its said given threshold level set at at least three volts and that is said at least a majority of floating gate charge levels are separated such that corresponding levels of current between the source and drain are separately detectable by said reading means.

Claim 13

The device according to claim 9 wherein the number of predetermined levels of electronic charge on the floating gate is exactly three, whereby at least two of these levels are net positive charge levels on the floating gate.