Logic synthesis system comprising a memory for a reduced number of translation rules

Claim 1

A logic synthesis system for synthesizing a design of a logic circuit in response to a system input signal representative of an input logical expression of said logic circuit to produce a system output signal representative of said design, said system comprising: memorizing means for memorizing a plurality of fundamental code signals representing fundamental codes, respectively, and a plurality of fundamental pattern signals representing fundamental patterns, respectively, said fundamental patterns being in one-to-one correspondence with said fundamental codes; first code producing means responsive to said system input signal for producing a first code signal representative of a first code corresponding to said input logical expression; judging means connected to said memorizing means and to said first code producing means for judging whether or not said first code is identical with none of said fundamental codes; second code producing means connected to said judging means for producing, when said judging means judges that said first code is identical with none of said fundamental codes, a second code signal representative of a second code which is a succession of selected ones of said fundamental codes that are selected in accordance with said first code; and translating means connected to said memorizing means, to said judging means, and to said second code producing means for translating, with reference to said selected ones of said fundamental codes and selected ones of said fundamental patterns that correspond to said selected ones of said fundamental codes, said second code signal into a translated signal when said judging means judges that said first code is identical with none of said fundamental codes, said translated signal representing a succession of said selected ones of said fundamental patterns, said translated signal being used as said system output signal; said judging means transferring said first code signal as a transferred code signal when said judging means judges that said first code is identical with a matching one of said fundamental codes that matches said first code; said translating means translating, with reference to said matching one of said fundamental codes and a particular one of said fundamental patterns that corresponds to said matching one of said fundamental codes, said transferred code signal into an alternative translated signal when said judging means judges that said first code is identical with said matching one of said fundamental codes, said alternative translated signal representing said particular one of said fundamental patterns, said alternative translated signal then being used as said system output signal.