Abstract An arithmetic circuit for calculating and accumulating absolute values of differences between first and second numerical values having a predetermined bit length and represented by 2's compliment notation is provided by a first inverter for inverting the second numerical value to produce an inverted value; a first adder receiving the first numerical value and the inverted numerical value and generating a sum as a first addition result; and a selector receiving the first addition result from first adder and an inverted addition result from the first adder via a second inverter and outputting a selected value based on the sign of the first addition result. A correcting value generating circuit generates a correcting value based on the sign of the first addition result. A second adder receives the selected value, the correcting value and a delayed addition result and generates a sum as a second addition result, which is output to a first delay circuit. The first delay circuit delays the second addition result by a predetermined delay and outputs the delayed addition result as an operation result while providing the delayed addition result to the second adder. Additional delay circuits responsive to a clock signal can be operatively coupled between the selector and the second adder to match the speeds of the selector and the first delay circuit.
An arithmetic circuit for calculating and accumulating absolute values of a difference between a first and a second numerical value having a predetermined bit length and represented by 2's complement notation and outputting an accumulation result as an operation result, said circuit comprising: first inverting means for inverting the second numerical value to produce an inverted value; first adder means for producing a sum of the first numerical value and said inverted value and outputting said sum as a first addition result; second inverting means for inverting the first addition result to output an inverted addition result; selecting means for selecting either one of said inverted addition result and said first addition result on the basis of a sign of said first addition result and outputting said one result as a selected value; correcting value generating means for outputting a correcting value on the basis of a sign of said first addition result; second adder means for producing a sum of said selected value, said correcting value and a delayed addition result and outputting said sum as a second addition result; and first delaying means for delaying said second addition result by a predetermined delay to produce said delayed addition result while outputting said delayed addition result as the operation result.
Claim 2
Dependent Claim
211 words
An arithmetic circuit for calculating and accumulating absolute values of a difference between a first and a second numerical value having a predetermined bit length and represented by 2's complement notation and outputting an accumulation result as an operation result, said circuit comprising: first inverting means for inverting the second numerical value to produce an inverted value; first adder means for producing a sum of the first numerical value and said inverted value and outputting said sum as a first addition result; second inverting means for inverting the first addition result to output an inverted addition result; selecting means for selecting either one of said inverted addition result and said first addition result on the basis of a sign of said first addition result and outputting said one result as a selected value; correcting value generating means for outputting a correcting value on the basis of a sign of said first addition result; second adder means for producing a sum of said selected value, said correcting value and a delayed addition result and outputting said sum as a second addition result; and first delaying means for delaying said second addition result by a predetermined delay to produce said delayed addition result while outputting said delayed addition result as the operation result.
Claim 3
Dependent Claim
36 words
An arithmetic circuit as claimed in claim 1, wherein said selecting means selects said inverted addition result when said first addition result is negative or said first addition result when said first addition result is positive.
Claim 4
Dependent Claim
29 words
An arithmetic circuit as claimed in claim 1, wherein said selecting means comprises a selector which receives a sign bit of said first addition result as a selection input.
Claim 5
Dependent Claim
27 words
An arithmetic circuit as claimed in claim 1, wherein said correcting value generating means comprises inverter means for inverting a sign bit of said first addition result.
Claim 6
Dependent Claim
37 words
An arithmetic circuit as claimed in claim 1, further comprising second delaying means for delaying said selected value and said correcting value by said predetermined delay and feeding said delayed selected value to said second adder means.