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EP0328063A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Absolute value calculating circuit having a single adder

Assignee: NEC Corp
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Filing: 1989-02-08
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Granted: —
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Expires: 2009-02-08
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Abstract

Abstract The absolute value calculating circuit produces an absolute value of a difference between a first and a second numerical value which have a predetermined bit length and are repre­sented by 2's complement notation. This circuit comprises first inverting means (13) for inverting the first numerical value to output an inverted numerical value, a first adder (14) for adding the second numerical value to the inverted numerical value to output an addition result, second inver­ting means (16) for inverting the addition result to output a first calculation result, a second adder (15) for adding 1 to the addition result to output a second calculation re­sult, and a selector (17) for selecting and delivering as an absolute value of a difference either one of the first and second calculation results by referencing a sign of the ad­dition result. The described circuit is simple in construc­tion and operable at a high speed and has a low power con­sumption.

Inventors

  • 👤 Toshiyuki C/O Nec Corporation Kanoh

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 02:18
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5055; G06F7/544; G06F2207/00; G06F2207/544; G06F2207/5442

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 135 words
An absolute value calculating circuit for producing an absolute value of a difference between a first and a second numerical value which have a predetermined bit length and are represented by 2's complement notation, comprising: first inverting means (13) for inverting the first numerical value to output an inverted numerical value; first adding means (14) for adding the second numerical value to the inverted numerical value to output an addition result; second inverting means (16) for inverting the addition result to output a first calculation result; second adding means (15) for adding 1 to the addition result to output a second calculation result; and selecting means (17) for selecting and delivering as an absolute value of a difference either one of the first and second calculation results by referencing a sign of the addition result.
Claim 2
Dependent Claim 135 words
An absolute value calculating circuit for producing an absolute value of a difference between a first and a second numerical value which have a predetermined bit length and are represented by 2's complement notation, comprising: first inverting means (13) for inverting the first numerical value to output an inverted numerical value; first adding means (14) for adding the second numerical value to the inverted numerical value to output an addition result; second inverting means (16) for inverting the addition result to output a first calculation result; second adding means (15) for adding 1 to the addition result to output a second calculation result; and selecting means (17) for selecting and delivering as an absolute value of a difference either one of the first and second calculation results by referencing a sign of the addition result.
Claim 3
Dependent Claim 33 words
A circuit as claimed in claim 1, wherein said selecting means selects the first calculation result when the addition result is negative and the second calculation result when the addition result is positive.
Claim 4
Dependent Claim 32 words
A circuit as claimed in claim 1 or 2, wherein said selecting means comprises a selector to which a sign bit of the addition result is applied as an input for selection.
Claim 5
Dependent Claim 206 words
A circuit as claimed in any of claims 1 to 3, wherein said second adding means comprises: inverting means for inverting a least significant bit (first bit) of the addition result having n bits to output a first bit of the second calculation result having n bits; first through (n-2)th AND gate means provided on a one-for-one basis with respect to the third through n-th bits of the addition result so that an i-th (1 ≦ i ≦ n-2) AND gate means outputs a result of AND operation of the first to (i+1)th bits of the addition result as an i-th carry bit; first Exclusive-OR gate means associated with the second bit of the addition result for outputting a result of Exclusive-OR operation of the first and second bits of the addition result as a second bit of the second calculation result; and second through (n-1)th Exclusive-OR gate means provided on a one-for-one basis with respect to the third through n-th bits of the addition result so that a j-th (2 ≦ j ≦ n-1) Exclusive-OR gate means outputs a result of Exclusive-OR operation of the (j-1)th carry bit and the (j+1)th bit of the addition result as a (j+1)th bit of the second calculation result.

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