Patent US5039885A successfully refreshed from Google Patents.
US5039885A
Expired / Lapsed
US
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Single function programmable logic array circuit
Assignee: Rohm Usa Inc
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Filing: 1986-04-25
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Granted: 1991-08-13
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Expires: 2006-04-25
Abstract
Abstract A programmable logic array which can produce single level logic or can produce multiple level logic through the use of internal feedback loops. A plurality of input lines intersect a plurality of term lines and can be programmable coupled to the term lines. A number of term lines provide a feedback input which intersects all of the term lines and can be programmably coupled to the tem lines. Teh input lines and the feedback input lines form a single matrix with the term lines.
Inventors
- 👤 Erich Goetting
- 👤 Yun Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
150 words
A programmable integrated logic circuit comprising: a plurality of term lines; a plurality of input lines intersecting said term lines; a plurality of feedback input lines intersecting said term lines, each of said feedback input lines originating from one of said term lines and being entirely contained within said circuit; and means for selectively coupling said input lines and feedback input lines to said term lines so that each term line acts as a single function logic gate output with the coupled input lines and feedback input lines being inputs to said single function logic gate, said means for selectively coupling including an MOS transistor having a gate coupled to one of said input and feedback input lines and a source coupled to a voltage potential, said means for selectively coupling further including second means for selectively coupling a drain of said MOS transistor to one of said term lines.
Claim 2
Dependent Claim
150 words
A programmable integrated logic circuit comprising: a plurality of term lines; a plurality of input lines intersecting said term lines; a plurality of feedback input lines intersecting said term lines, each of said feedback input lines originating from one of said term lines and being entirely contained within said circuit; and means for selectively coupling said input lines and feedback input lines to said term lines so that each term line acts as a single function logic gate output with the coupled input lines and feedback input lines being inputs to said single function logic gate, said means for selectively coupling including an MOS transistor having a gate coupled to one of said input and feedback input lines and a source coupled to a voltage potential, said means for selectively coupling further including second means for selectively coupling a drain of said MOS transistor to one of said term lines.
Claim 3
Dependent Claim
150 words
A programmable integrated logic circuit comprising: a plurality of term lines; a plurality of input lines intersecting said term lines; a plurality of feedback input lines intersecting said term lines, each of said feedback input lines originating from one of said term lines and being entirely contained within said circuit; and means for selectively coupling said input lines and feedback input lines to said term lines so that each term line acts as a single function logic gate output with the coupled input lines and feedback input lines being inputs to said single function logic gate, said means for selectively coupling including an MOS transistor having a drain coupled to one of said term lines and a source coupled to a voltage potential, said means for selectively coupling further including second means for selectively coupling a gate of said MOS transistor to one of said input and feedback input lines.
Claim 4
Dependent Claim
150 words
A programmable integrated logic circuit comprising: a plurality of term lines; a plurality of input lines intersecting said term lines; a plurality of feedback input lines intersecting said term lines, each of said feedback input lines originating from one of said term lines and being entirely contained within said circuit; and means for selectively coupling said input lines and feedback input lines to said term lines so that each term line acts as a single function logic gate output with the coupled input lines and feedback input lines being inputs to said single function logic gate, said means for selectively coupling including an MOS transistor having a drain coupled to one of said term lines and a source coupled to a voltage potential, said means for selectively coupling further including second means for selectively coupling a gate of said MOS transistor to one of said input and feedback input lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-12 | 1995-02-11 | 1995-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-12 | 1999-02-11 | 1999-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-12 | 2003-02-11 | 2003-08-13 | $7700.00 | Window Closed / Lapsed |