US5039882A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Address decoder circuit for non-volatile memory
Assignee: Sony Corp
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Filing: 1989-10-13
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Granted: 1991-08-13
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Expires: 2009-10-13
Abstract
Abstract An address decoder circuit adapted for enabling electrical erasure in a non-volatile memory without the necessity of numerically increasing the component elements, wherein the direction of application (polarity) of a supply voltage during an erasing operation to a decoding logic gate portion comprising a load MOS transistor and an address input MOS transistor is rendered different from that during a writing or reading operation, and a third potential is applied to the power terminal proximate to the address input MOS transistor and also to the power terminal of a buffer, whereby the third potential is outputted to prevent erasure in the state of non-selection. The resistance of load means is changed to be greater in a writing operation for reducing the power consumption during the writing operation and minimizing the dimensions of component elements. And in a voltage supply circuit, for the purpose of outputting a desired voltage without providing any additional circuit which may consume great power or without causing any level reduction of a first or write voltage, a MOS transistor for outputting the first voltage is controlled in response to a signal obtained by boosting the voltage of a control signal through a voltage multiplier.
Inventors
- 👤 Hideki Arakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:18
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
202 words
An address decoder circuit for a non-volatile memory which produces, in a selection state, a first potential during a reading operation or a second potential greater in absolute value than the first potential during a writing operation, said address decoder circuit comprising: a load MOS transistor connected at one end thereof to a first terminal; one or more series-connected address input MOS transistors receiving address signals at gates thereof and coupled between the other end of said load MOS transistor and a second terminal; and a buffer receiving as an input a signal from a node of said load MOS transistor and said address input MOS transistor, and also receiving as a supply voltage the voltage between a third terminal and a reference potential terminal; wherein, during a reading operation, the first potential is outputted from the selected buffer by applying the first potential to both the first and third terminals; during a writing operation, the second potential is outputted from the selected buffer by applying the second potential to both the first and third terminals; and during an erasing operation, a third potential is outputted in a non-selection state by applying a third potential to both the second and third terminals.
Claim 2
Dependent Claim
202 words
An address decoder circuit for a non-volatile memory which produces, in a selection state, a first potential during a reading operation or a second potential greater in absolute value than the first potential during a writing operation, said address decoder circuit comprising: a load MOS transistor connected at one end thereof to a first terminal; one or more series-connected address input MOS transistors receiving address signals at gates thereof and coupled between the other end of said load MOS transistor and a second terminal; and a buffer receiving as an input a signal from a node of said load MOS transistor and said address input MOS transistor, and also receiving as a supply voltage the voltage between a third terminal and a reference potential terminal; wherein, during a reading operation, the first potential is outputted from the selected buffer by applying the first potential to both the first and third terminals; during a writing operation, the second potential is outputted from the selected buffer by applying the second potential to both the first and third terminals; and during an erasing operation, a third potential is outputted in a non-selection state by applying a third potential to both the second and third terminals.
Claim 3
Dependent Claim
48 words
An address decoder circuit according to claim 1, wherein a reference potential is outputted in a selection state during an erasing operation, so that a negative voltage is applied to the control gate of the non-volatile memory to allow injection of positive holes into the floating gate thereof.
Claim 4
Dependent Claim
23 words
An address decoder circuit according to claim 1, wherein the back gate of said load MOS transistor is connected to the third terminal.
Claim 5
Dependent Claim
65 words
An address decoder circuit for a non-volatile memory which comprises load means and MOS transistors supplied with address signals and receives a variable supply voltage whose absolute value in a writing operation is greater than that in a reading operation, wherein said load means is composed of a variable resistance means whose resistance becomes lower in the reading operation and higher in the writing operation.
Claim 6
Dependent Claim
65 words
An address decoder circuit for a non-volatile memory which comprises load means and MOS transistors supplied with address signals and receives a variable supply voltage whose absolute value in a writing operation is greater than that in a reading operation, wherein said load means is composed of a variable resistance means whose resistance becomes lower in the reading operation and higher in the writing operation.
Claim 7
Dependent Claim
49 words
An address decoder circuit according to claim 4, wherein the resistance of said load means is controlled by resistance control means in such a manner as to vary in conformity with the change in the variable supply voltage within a range between a write voltage and a read voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-12 | 1995-02-11 | 1995-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-12 | 1999-02-11 | 1999-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-12 | 2003-02-11 | 2003-08-13 | $7700.00 | Window Closed / Lapsed |