Patent US5039872A successfully refreshed from Google Patents.
US5039872A
Expired / Lapsed
US
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Digitally synthesized audio frequency voltage source
Assignee: United States Department of Commerce
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Filing: 1989-09-28
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Granted: 1991-08-13
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Expires: 2009-09-28
Abstract
Abstract A method and apparatus for accurately generating a digitally synthesized sinusoidal voltage is started by storing digital values for sine waveforms in a read only memory. A first and second digital to analog converters are connected to the read only memory through latches. The outputs of the first and second digital to analog converters are alternatively switched between the inverting input and the non-inverting input of an operational amplifier such that one of the first and second digital to analog converter is connected to the inverting input while the other is connected to the non-inverting input. The output of the operational amplifier is connected to the inverting input through a variable capacitance, the feedback being determined by the one of the first and second digital to analog converter connected to the inverting input. A clock is used to control the connection of the first and second digital to analog converter to the inverting input and to control the determination of the feedback.
Inventors
- 👤 Nile M. Oldham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:54
CPC Classifications
G; G06; G06J; G06J1/00; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2836; G01R31/2839; G01R31/2841; G01R35/00; G01R35/005
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
337 words
A digitally synthesized source for synthesizing a sinusoidal voltage waveform comprising: a read only memory storing digital values representing sine waveforms; clock means for generating first and second pulse trains such that while said first pulse train is high, said second pulse train is low and while said second pulse train is high, the first pulse train is low; first latch means connected to said clock means and said read only memory and responsive to said first pulse train to provide as output digital values stored in said read only memory; a first converter means connected to said first latch means for receiving and converting digital values stored in said read only memory into a first output current step signal in response to pulses of said first pulse train; second latch means connected to said clock means and said read only memory and responsive to said second pulse train to provide as output digital values stored in said read only memory; a second converter means connected to said second latch means for receiving and converting digital values stored in said read only memory into a second output current step signal in response to pulses of the second pulse train; an operational amplifier having an inverting input, a non-inverting input and an output; switch means for alternatively connecting said first converter means and said second converter means to said inverting input and said non-inverting input under control of said first and second pulse trains such that one of said first and said second current step signals is connected to said inverting input while the other is connected to said non-inverting input; and a feedback connection between said output and said inverting input of said operational amplifier through a variable capacitance, said variable capacitance being set to a low value for eliminating frequency components above 10-20 MHZ in the voltage waveform and for trimming a bandwidth of the operational amplifier so that a RMS value of the voltage waveform is flat within the audio-frequency range of the voltage waveform.
Claim 2
Dependent Claim
337 words
A digitally synthesized source for synthesizing a sinusoidal voltage waveform comprising: a read only memory storing digital values representing sine waveforms; clock means for generating first and second pulse trains such that while said first pulse train is high, said second pulse train is low and while said second pulse train is high, the first pulse train is low; first latch means connected to said clock means and said read only memory and responsive to said first pulse train to provide as output digital values stored in said read only memory; a first converter means connected to said first latch means for receiving and converting digital values stored in said read only memory into a first output current step signal in response to pulses of said first pulse train; second latch means connected to said clock means and said read only memory and responsive to said second pulse train to provide as output digital values stored in said read only memory; a second converter means connected to said second latch means for receiving and converting digital values stored in said read only memory into a second output current step signal in response to pulses of the second pulse train; an operational amplifier having an inverting input, a non-inverting input and an output; switch means for alternatively connecting said first converter means and said second converter means to said inverting input and said non-inverting input under control of said first and second pulse trains such that one of said first and said second current step signals is connected to said inverting input while the other is connected to said non-inverting input; and a feedback connection between said output and said inverting input of said operational amplifier through a variable capacitance, said variable capacitance being set to a low value for eliminating frequency components above 10-20 MHZ in the voltage waveform and for trimming a bandwidth of the operational amplifier so that a RMS value of the voltage waveform is flat within the audio-frequency range of the voltage waveform.
Claim 3
Dependent Claim
19 words
The digitally synthesized source according to claim 1 also including connector means for connecting said non-inverting input to ground.
Claim 4
Dependent Claim
15 words
The digitally synthesized source according to claim 1 wherein said switch means includes CMOS switches.
Claim 5
Dependent Claim
23 words
The digitally synthesized source according to claim 1 wherein said first and said second converter means includes a multiplying digital to analog converter.
Claim 6
Dependent Claim
16 words
The digitally synthesized source according to claim 1 wherein said clock means includes an internal clock.
Claim 7
Dependent Claim
16 words
The digitally synthesized source according to claim 1 wherein said clock means includes an external clock.
Claim 8
Dependent Claim
218 words
In a digitally synthesized alternating current voltage source for synthesizing a sinusoidal voltage waveform including a read only memory storing digital values representing sine waveforms; a first multiplying digital to analog converter connected to said read only memory through a first latch means; a second multiplying digital to analog converter connected to said read only memory through a second latch means; an operational amplifier having a inverting input, a non-inverting input and an output; switch means for alternatively connecting said first multiplying digital to analog converter and said second multiplying digital to analog converter to said inverting input and said non-inverting input such that one of said first multiplying digital to analog converter and said second multiplying digital to analog converter is connected to said inverting input while the other is connected to said non-inverting input; and clock means connected to said switch means for controlling connection of said first and second multiplying digital to analog converters to said inverting input; the improvement comprising: a feedback connection between the output and the inverting input of said operational amplifier through a variable capacitor which is set to a low capacitance value for eliminating frequency components above 10-20 MHZ in the voltage waveform and to flatten the RMS gain of the voltage waveform within the audiofrequency range of the waveform.
Claim 9
Dependent Claim
218 words
In a digitally synthesized alternating current voltage source for synthesizing a sinusoidal voltage waveform including a read only memory storing digital values representing sine waveforms; a first multiplying digital to analog converter connected to said read only memory through a first latch means; a second multiplying digital to analog converter connected to said read only memory through a second latch means; an operational amplifier having a inverting input, a non-inverting input and an output; switch means for alternatively connecting said first multiplying digital to analog converter and said second multiplying digital to analog converter to said inverting input and said non-inverting input such that one of said first multiplying digital to analog converter and said second multiplying digital to analog converter is connected to said inverting input while the other is connected to said non-inverting input; and clock means connected to said switch means for controlling connection of said first and second multiplying digital to analog converters to said inverting input; the improvement comprising: a feedback connection between the output and the inverting input of said operational amplifier through a variable capacitor which is set to a low capacitance value for eliminating frequency components above 10-20 MHZ in the voltage waveform and to flatten the RMS gain of the voltage waveform within the audiofrequency range of the waveform.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-12 | 1995-02-11 | 1995-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-12 | 1999-02-11 | 1999-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-12 | 2003-02-11 | 2003-08-13 | $7700.00 | Window Closed / Lapsed |