Patent US4275321A successfully refreshed from Google Patents.
US5038215A
Expired / Lapsed
US
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Imaging apparatus with improved synchronization
Assignee: Teledyne UK Ltd
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Filing: 1990-01-17
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Granted: 1991-08-06
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Expires: 2010-01-17
Abstract
Abstract A CCD imaging array includes one or more shift registers. By injecting a charge packet at one end of the shift register, at times related to the start of line read out, then the charge packet reaches the other end of the shift register at the end of the line period. Thus the shift register can be used to generate line synchronization signals. The technique can also be applied for more complex waveform generation and for field generation.
Inventors
- 👤 Kevin A. D. Hadfield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:59
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/713
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
174 words
Solid-state imaging apparatus comprising; an imaging array having a region on which an image is formed, means to produce electrical charges representing said image, and output means to produce output signals representative of said image from said electrical charges; shift register means having clock input means, input port means, and an output port; means for introducing at least one packet of charge into said input port means of said shift register means; clock means for applying clock signals to said clock input means for said shift register means, said clock means for applying clock signals causing said electrical charges and said at least one packet of charge to be clocked respectively through said imaging array and said shift register means at rates which are related to one another; means for obtaining synchronising output signals from said output port, said synchronising output signals being delayed versions of said at least one packet of charge introduced into said input port means; and means for using said synchronising output signals as synchronising waveforms for said imaging array.
Claim 2
Dependent Claim
174 words
Solid-state imaging apparatus comprising; an imaging array having a region on which an image is formed, means to produce electrical charges representing said image, and output means to produce output signals representative of said image from said electrical charges; shift register means having clock input means, input port means, and an output port; means for introducing at least one packet of charge into said input port means of said shift register means; clock means for applying clock signals to said clock input means for said shift register means, said clock means for applying clock signals causing said electrical charges and said at least one packet of charge to be clocked respectively through said imaging array and said shift register means at rates which are related to one another; means for obtaining synchronising output signals from said output port, said synchronising output signals being delayed versions of said at least one packet of charge introduced into said input port means; and means for using said synchronising output signals as synchronising waveforms for said imaging array.
Claim 3
Dependent Claim
28 words
Apparatus as claimed in claim 1, wherein said imaging array is an M×N array in which N is the number of columns and M the number of rows.
Claim 4
Dependent Claim
21 words
Apparatus as claimed in claim 1, wherein said synchronising output signals are useable as line synchronisation signals for said imaging array.
Claim 5
Dependent Claim
39 words
Apparatus as claimed in claim 1, wherein said shift register means is adapted to be clocked once every line period of said imaging array, and said synchronising output signals are useable as field synchronisation signals for said imaging array.
Claim 6
Dependent Claim
57 words
Apparatus as claimed in claim 1, in which said imaging array comprises a line readout register having a first output terminal from which a second output signal is obtained, a dummy line read-out register having a second output terminal from which a third output signal is obtained, said shift register means comprising said dummy line read-out register.
Claim 7
Dependent Claim
66 words
Apparatus as claimed in claim 5 comprising means for combining said second and third output signals to produce a fourth output signal containing both image information and synchronising information, said means for combining comprising a first input port coupled to said first output terminal, a second input port coupled to said second output terminal, and an output port from which said fourth output signal is obtained.
Claim 8
Dependent Claim
39 words
Apparatus as claimed in claim 5 in which, during each line period of said imaging array, said at least one packet of charge comprises a single packet of charge fed into a single location of said dummy readout register.
Claim 9
Dependent Claim
54 words
Apparatus as claimed in claim 5 in which, during each line period of said imaging array, said at least one packet of charge comprises a plurality of separate charge packets, said plurality of separate charge packets being fed into a single location of said dummy readout register at different times during said line period.
Claim 10
Dependent Claim
50 words
Apparatus as claimed in claim 5 in which, during each line period, said at least one packet of charge comprises a plurality of separate charge packets, said plurality of separate charge packets being fed into different locations of said dummy readout register at different times during a single line period.
Claim 11
Dependent Claim
48 words
Apparatus as claimed in claim 1 in which said imaging array comprises a line readout register having a first output terminal from which a second output signal is obtained, said shift register comprising said line readout register, said second output signal containing both image information and synchronising information.
Claim 12
Dependent Claim
32 words
Apparatus as claimed in claim 10 in which said separate charge packets representing synchronising waveforms are of greater magnitude than the magnitude of the largest possible said electrical charge representing said image.
Claim 13
Dependent Claim
45 words
Apparatus as claimed in claim 11 in which, during each line period of said imaging array, said at least one packet of charge comprises a single packet of charge, said single packet of charge being fed into a single location of said line readout register.
Claim 14
Dependent Claim
50 words
Apparatus as claimed in claim 11 in which, during each line period of said imaging array, said at least one packet of charge comprises a plurality of separate charge packets, said plurality of separate charge packets being fed into a single location of said line readout register at different times.
Claim 15
Dependent Claim
46 words
Apparatus as claimed in claim 11 in which, during each line period of said imaging array, said at least one packet of charge comprises a plurality of separate charge packets, said plurality of separate charge packets being fed into different locations of said line readout register.
Claim 16
Dependent Claim
119 words
Apparatus as claimed in claim 11 in which said line readout shift register is adapted to enable information to be read therefrom in either direction, each end of said line readout shift register having a respective readout amplifier adapted to read out information from said line readout shift register, only one of said amplifiers being used according to the direction of clocking of said line readout shift register, said at least one packet of charge being fed into a single location of said line readout shift register, said single location comprising that location of said line readout shift register at the opposite end thereof from that location from which data is read out of said line readout shift register.
Claim 17
Dependent Claim
13 words
Apparatus as claimed in claim 1 wherein said array is a CCD array.
Claim 18
Dependent Claim
149 words
Apparatus adapted to provide synchronisation waveform signals for an imaging array, said apparatus comprising shift register means having clock input means, input port means, and an output port, means for introducing at least one packet of charge into said input port means of said shift register means; clock means for applying clock signals to said clock input means of said shift register means, said clock means causing said at least one packet of charge to be clocked through said shift register means; said shift register means having a predetermined number of stages such that said at least one packet of charge introduced into said input port means emerges from said output port at at least one predetermined later time period so as to provide said synchronisation waveform signals, said synchronisation waveform signals being delayed versions of said at least one packet of charge introduced into said input port means.
Claim 19
Dependent Claim
149 words
Apparatus adapted to provide synchronisation waveform signals for an imaging array, said apparatus comprising shift register means having clock input means, input port means, and an output port, means for introducing at least one packet of charge into said input port means of said shift register means; clock means for applying clock signals to said clock input means of said shift register means, said clock means causing said at least one packet of charge to be clocked through said shift register means; said shift register means having a predetermined number of stages such that said at least one packet of charge introduced into said input port means emerges from said output port at at least one predetermined later time period so as to provide said synchronisation waveform signals, said synchronisation waveform signals being delayed versions of said at least one packet of charge introduced into said input port means.
Claim 20
Dependent Claim
39 words
Apparatus as claimed in claim 17 in which said at least one packet of charge comprises a plurality of packets of charge, each said packet of charge being injected into a predetermined different element of said shift register means.
Claim 21
Dependent Claim
42 words
Apparatus as claimed in claim 17, in which said at least one packet of charge comprises a plurality of packets of charge, each said packet of charge being injected into a single predetermined element of said shift register means at different times.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-05 | 1995-02-04 | 1995-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-05 | 1999-02-04 | 1999-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-05 | 2003-02-04 | 2003-08-06 | $7700.00 | Window Closed / Lapsed |