US5036224A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single ended MOS to ECL output buffer
Assignee: National Semiconductor Corp
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Filing: 1990-03-01
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Granted: 1991-07-30
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Expires: 2010-03-01
Abstract
Abstract An output buffer circuit which converts CMOS logic levels to ECL logic levels. ECL high and ECL low level voltage signals are generated by a reference network. A switch responds to the status of a pair of complementary CMOS inputs to selectively connect one of the ECL voltage signals to an ECL load.
Inventors
- 👤 Dennis L. Wendell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:52
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509; H03K19/017518
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
368 words
An output buffer circuit for converting first and second complementary CMOS level input signals to an ECL level output signal, the circuit comprising: (a) first ECL means for generating an ECL high voltage level signal; (b) second ECL means for generating an ECL low voltage level signal; (c) an output gain stage responsive to the output of the switching means for providing gain to the ECL level output signal; (d) a npn transistor; (e) a first PMOS transistor having its gate connected to receive said first complementary CMOS level input signal, its drain connected to receive the ECL low level voltage signal, and its source connected to the output gain stage, such that said first PMOS transistor turns on when said first complementary CMOS level input signal is low, thereby effectively connecting said ECL low level voltage to said output gain stage; (f) a second PMOS transistor having its gate connected to receive said second complementary CMOS level input signal, its source connected to receive said ECL high level voltage, and its drain connected to the output gain stage, such that said second PMOS transistor turns on when said second complementary CMOS level input signal goes low thereby effectively connecting said ECL high level voltage to said output gain stage; (g) a third PMOS transistor having its gate connected to receive said first complementary CMOS level input signal, its drain connected to the output gain stage, and its source connected to the base of said npn transistor, such that said third PMOS transistor turns on when said first complementary CMOS level input signal is slow thereby inhibiting said npn transistor from conducting; and (h) a fourth PMOS transistor having its gate connected to receive said second complementary CMOS level input signal, its drain connected to the base of said npn transistor, and its source commonly connected to both the collector of said npn transistor and a first reference voltage, such that said fourth PMOS transistor turns on when said second complementary CMOS level input signal goes low, such that said npn transistor conducts and shortens the rise time needed for said output gain stage to transition from said ECL low level voltage to said ECL high level voltage.
Claim 2
Dependent Claim
368 words
An output buffer circuit for converting first and second complementary CMOS level input signals to an ECL level output signal, the circuit comprising: (a) first ECL means for generating an ECL high voltage level signal; (b) second ECL means for generating an ECL low voltage level signal; (c) an output gain stage responsive to the output of the switching means for providing gain to the ECL level output signal; (d) a npn transistor; (e) a first PMOS transistor having its gate connected to receive said first complementary CMOS level input signal, its drain connected to receive the ECL low level voltage signal, and its source connected to the output gain stage, such that said first PMOS transistor turns on when said first complementary CMOS level input signal is low, thereby effectively connecting said ECL low level voltage to said output gain stage; (f) a second PMOS transistor having its gate connected to receive said second complementary CMOS level input signal, its source connected to receive said ECL high level voltage, and its drain connected to the output gain stage, such that said second PMOS transistor turns on when said second complementary CMOS level input signal goes low thereby effectively connecting said ECL high level voltage to said output gain stage; (g) a third PMOS transistor having its gate connected to receive said first complementary CMOS level input signal, its drain connected to the output gain stage, and its source connected to the base of said npn transistor, such that said third PMOS transistor turns on when said first complementary CMOS level input signal is slow thereby inhibiting said npn transistor from conducting; and (h) a fourth PMOS transistor having its gate connected to receive said second complementary CMOS level input signal, its drain connected to the base of said npn transistor, and its source commonly connected to both the collector of said npn transistor and a first reference voltage, such that said fourth PMOS transistor turns on when said second complementary CMOS level input signal goes low, such that said npn transistor conducts and shortens the rise time needed for said output gain stage to transition from said ECL low level voltage to said ECL high level voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-29 | 1995-01-28 | 1995-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-29 | 1999-01-28 | 1999-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-29 | 2003-01-28 | 2003-07-30 | $7700.00 | Window Closed / Lapsed |