US4704549A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS to ECL converter-buffer
Assignee: Intellectual Ventures I LLC
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Filing: 1986-10-24
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Granted: 1987-11-03
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Expires: 2006-10-24
Abstract
Abstract The circuit of the present invention converts CMOS logic level signals to corresponding ECL logic level signals to permit the coupling of CMOS and ECL devices. In addition, the present invention maintains a relatively constant impedance as the logic levels on its output change. The circuit has an input terminal connectable to a source of a first set of logic signals and an output terminal connectable to a device that is responsive to a second set of logic level signals. First and second power terminals are provided for connection to first and second power supplies, respectively. A transistor of first conductivity type having first, second and gate terminals is provided with the gate terminal connected to the input terminal and the first terminal connected to the first power supply terminal. A second transistor of opposite conductivity type having a first, second and gate terminal is provided with the gate terminal of the second transistor connected to the second terminal of the first transistor. The second terminal of the second transistor is connected to the output terminal and the first terminal of the second transistor is connected to the second power supply terminal. A saturation means is connected between the gate terminal and the second terminal of the second transistor. The saturation means is responsive to the signal on the input terminal for saturating the second transistor in an "ON" state when the logic level 0 is applied to the input terminal.
Inventors
- 👤 Ikuo J. Sanwo
- 👤 Donald K. Lauffer
- 👤 Donald G. Tipon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
186 words
A converter-buffer for converting a first set of logic level signals to a second set of logic level signals comprising: an input terminal connectable to a source of said first set of logic level signals; an output terminal connectable to a device responsive to said second set of logic level signals; first and second power terminals for connection to first and second power supplies, respectively; a transistor of first conductivity type having first, second and gate terminals, said gate terminal connected to said input terminal, said first terminal connected to said first power terminal; a second transistor of opposite conductivity type having first, second and gate terminals, the gate terminal of said second transistor connected to the second terminal of said first transistor, the second terminal of said second transistor connected to said output terminal, and the first terminal of said second transistor connected to said second power supply terminal; and saturation means connected between the gate terminal and the second terminal of said second transistor, said saturation means responsive to the signal on said input terminal for saturating said second transistor in an "ON" state.
Claim 2
Dependent Claim
186 words
A converter-buffer for converting a first set of logic level signals to a second set of logic level signals comprising: an input terminal connectable to a source of said first set of logic level signals; an output terminal connectable to a device responsive to said second set of logic level signals; first and second power terminals for connection to first and second power supplies, respectively; a transistor of first conductivity type having first, second and gate terminals, said gate terminal connected to said input terminal, said first terminal connected to said first power terminal; a second transistor of opposite conductivity type having first, second and gate terminals, the gate terminal of said second transistor connected to the second terminal of said first transistor, the second terminal of said second transistor connected to said output terminal, and the first terminal of said second transistor connected to said second power supply terminal; and saturation means connected between the gate terminal and the second terminal of said second transistor, said saturation means responsive to the signal on said input terminal for saturating said second transistor in an "ON" state.
Claim 3
Dependent Claim
174 words
A converter-buffer for converting a first set of logic level signals to a second set of logic level signals comprising: an input terminal connectable to a source of said first set of logic level signals; an output terminal connectable to a device responsive to said second set of logic level signals; first and second power terminals for connection to first and second power suplies, respectively; a first transistor of first conductivity type having first, second and gate terminals, said gate terminal connected to said input terminal, said first terminal connected to said first power terminal; and second and third transistors of opposite conductivity type having first, second and gate terminals, the gate terminal of said third transistor connected to said input terminal, the first terminal of said third transistor connected to the gate of said second transistor and to the second terminal of said first transistor, the second terminal of said second and said third transistors connected to said output terminal, the first terminal of said second transistor connected to said second power terminal.
Claim 4
Dependent Claim
174 words
A converter-buffer for converting a first set of logic level signals to a second set of logic level signals comprising: an input terminal connectable to a source of said first set of logic level signals; an output terminal connectable to a device responsive to said second set of logic level signals; first and second power terminals for connection to first and second power suplies, respectively; a first transistor of first conductivity type having first, second and gate terminals, said gate terminal connected to said input terminal, said first terminal connected to said first power terminal; and second and third transistors of opposite conductivity type having first, second and gate terminals, the gate terminal of said third transistor connected to said input terminal, the first terminal of said third transistor connected to the gate of said second transistor and to the second terminal of said first transistor, the second terminal of said second and said third transistors connected to said output terminal, the first terminal of said second transistor connected to said second power terminal.
Claim 5
Dependent Claim
161 words
A converter-buffer for converting CMOS logic level signals to ECL logic level signals comprising: an input terminal and an output terminal, said input terminal connectable to a source of CMOS logic level signals, said output terminal connectable to an ECL device; a first terminal for connection to a first power supply; a second terminal for connection to a second power supply; an N channel transistor having source, drain, and gate electrodes, said gate electrode connected to said input terminal, said source electrode connected to said first terminal; and second and third P channel transistors each having source, drain, and gate electrodes, the gate electrode of said third transistor connected to said input terminal, the source of said third transistor connected to the gate of said second transistor and to the drain of said first transistor; the drain of said second and said third transistors connected to said output terminal, the source electrode of said second transistor connected to said second terminal.
Claim 6
Dependent Claim
161 words
A converter-buffer for converting CMOS logic level signals to ECL logic level signals comprising: an input terminal and an output terminal, said input terminal connectable to a source of CMOS logic level signals, said output terminal connectable to an ECL device; a first terminal for connection to a first power supply; a second terminal for connection to a second power supply; an N channel transistor having source, drain, and gate electrodes, said gate electrode connected to said input terminal, said source electrode connected to said first terminal; and second and third P channel transistors each having source, drain, and gate electrodes, the gate electrode of said third transistor connected to said input terminal, the source of said third transistor connected to the gate of said second transistor and to the drain of said first transistor; the drain of said second and said third transistors connected to said output terminal, the source electrode of said second transistor connected to said second terminal.
References Cited (Backward Citations)
DE2740799A1
Cited
US4563601A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-02 | 1991-05-04 | 1991-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-02 | 1995-05-04 | 1995-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-02 | 1999-05-04 | 1999-11-03 | $7700.00 | Window Closed / Lapsed |