Low power, TTL level CMOS input buffer with hysteresis

Claim 2

An input circuit comprising: a first transistor of a first conductivity type having its source connected to a first reference voltage, its gate connected to an input signal, and having a drain; second and third transistors of an opposite conductivity type having their source/drain paths connected in series between the drain of said first transistor and a common potential, and having their gates connected to the input signal; an invertor having its input connected to the drain of said first transistor, and having an output; a fourth transistor of said first conductivity type having its gate connected to the output, its drain connected to the series connection between said second and third transistors, and having its source connected to a second reference voltage; and wherein the second reference voltage is higher than the first reference voltage.

Claim 3

An input circuit comprising: a first transistor of a first conductivity type having its source connected to a first reference voltage, its gate connected to an input signal, and having a drain; second and third transistors of an opposite conductivity type having their source/drain paths connected in series between the drain of said first transistor and a common potential, and having their gates connected to the input signal; an invertor having its input connected to the drain of said first transistor, and having an output; a fourth transistor of said first conductivity type having its gate connected to the output, its drain connected to the series connection between said second and third transistors, and having its source connected to a second reference voltage; and wherein the second reference voltage is lower than the first reference voltage.

Claim 4

An input circuit comprising: a first transistor of a first conductivity type having its source connected to a first reference voltage, its gate connected to an input signal, and having a drain; second and third transistors of an opposite conductivity type having their source/drain paths connected in series between the drain of said first transistor and a common potential, and having their gates connected to the input signal; an invertor having its input connected to the drain of said first transistor, and having an output; a fourth transistor of said first conductivity type having its gate connected to the output, its drain connected to the series connection between said second and third transistors, and having its source connected to a second reference voltage; and wherein the second reference voltage is lower than the first reference voltage.

Claim 5

An input circuit comprising: a first transistor of a first conductivity type having its source connected to a first reference voltage, its gate connected to an input signal, and having a drain; second and third transistors of an opposite conductivity type having their source/drain paths connected in series between the drain of said first transistor and a common potential, and having their gates connected to the input signal; an invertor having its input connected to the drain of said first transistor, and having an output; a fourth transistor of said first conductivity type having its gate connected to the output, its drain connected to the series connection between said second and third transistors, and having its source connected to a second reference voltage; and a first pull-up transistor of the opposite conductivity type having its drain connected to a voltage supply, its gate connected to a voltage reference generator circuit and its source connected to the source of the first transistor.

Claim 6

An input circuit comprising: a first transistor of a first conductivity type having its source connected to a first reference voltage, its gate connected to an input signal, and having a drain; second and third transistors of an opposite conductivity type having their source/drain paths connected in series between the drain of said first transistor and a common potential, and having their gates connected to the input signal; an invertor having its input connected to the drain of said first transistor, and having an output; a fourth transistor of said first conductivity type having its gate connected to the output, its drain connected to the series connection between said second and third transistors, and having its source connected to a second reference voltage; and a first pull-up transistor of the opposite conductivity type having its drain connected to a voltage supply, its gate connected to a voltage reference generator circuit and its source connected to the source of the first transistor.

Claim 7

The circuit of claim 3 further comprising: a second pull-up transistor of the first conductivity type having its source connected to the voltage supply, its drain connected to the input of the inverter, and its gate connected to the output.

Claim 8

The circuit of claim 4 further comprising: logic circuitry having a logic input and coupled to the input of the inverter in such a manner that the inverter is also responsive to the state of the logic input of the logic circuitry.

Claim 9

The circuit of claim 5 wherein said logic circuitry comprises: a first logic transistor of the first conductivity type having its gate connected to the logic input, and its source/drain path connected in series between the voltage supply and the input of the inverter; and a second logic transistor of the second conductivity type having its gate connected to the logic input, and its source/drain path connected in series between the drain of the first transistor and the common potential.

Claim 10

The circuit of claim 5 wherein said logic circuitry comprises: a first logic transistor of the first conductivity type having its gate connected to the logic input, and its source/drain path connected in series between the voltage supply and the drain of the first pull-up transistor; and a second logic transistor of the second conductivity type having its gate connected to the logic input, and its source/drain path connected in series between the input of the inverter and the common potential.

Claim 11

The circuit of claim 5 wherein said logic circuitry comprises: a first logic transistor of the first conductivity type having its gate connected to the logic input, and its source/drain path connected in series between the source of the first pull-up transistor and the source of the first transistor; and a second logic transistor of the second conductivity type having its gate connected to the logic input, and its source/drain path connected in series between the input of the inverter and the common potential.

Claim 12

The circuit of claim 3 further comprising: a second pull-up transistor of the first conductivity type having its source connected to the second reference voltage, its drain connected to the input of the inverter, and having its gate connected to the output.

Claim 13

The circuit of claim 3 wherein the first transistor and the fourth transistor are p-channel MOS transistors and the second transistor, third transistor, and the pull-up transistor are n-channel MOS transistors.

Claim 14

An input circuit comprising: a first transistor of a first conductivity type having its source connected to a first reference voltage, its gate connected to an input signal, and having a drain; second and third transistors of an opposite conductivity type having their source/drain paths connected in series between the drain of said first transistor and a common potential, and having their gates connected to the input signal; an invertor having its input connected to the drain of said first transistor, and having an output; a fourth transistor of said first conductivity type having its gate connected to the output, its drain connected to the series connection between said second and third transistors, and having its source connected to a second reference voltage; and a first pull-up transistor of the opposite conductivity type having its drain and gate connected to a voltage supply, and its source connected to the source of the first transistor.

Claim 15

An input circuit comprising: a first transistor of a first conductivity type having its source connected to a first reference voltage, its gate connected to an input signal, and having a drain; second and third transistors of an opposite conductivity type having their source/drain paths connected in series between the drain of said first transistor and a common potential, and having their gates connected to the input signal; an invertor having its input connected to the drain of said first transistor, and having an output; a fourth transistor of said first conductivity type having its gate connected to the output, its drain connected to the series connection between said second and third transistors, and having its source connected to a second reference voltage; and a first pull-up transistor of the opposite conductivity type having its drain and gate connected to a voltage supply, and its source connected to the source of the first transistor.

Claim 16

The circuit of claim 11 further comprising: a second pull-up transistor of the first conductivity type having its source connected to the voltage supply, its drain connected to the input of the inverter, and its gate connected to the output.

Claim 17

The circuit of claim 11 further comprising: a second pull-up transistor of the first conductivity type having its source connected to the second reference voltage, its drain connected to the input of the inverter, and its gate connected to the output.

Claim 18

The circuit of claim 11 wherein the first transistor and the fourth transistor are p-channel MOS transistors and the second transistor, third transistor, and the pull-up transistor are n-channel MOS transistors.

Claim 19

An input circuit comprising: a pull-up transistor having its source/drain path connected in series between a first reference voltage and an intermediate output node, and having its gate connected to an input signal, its source/drain path being conductive responsive to the input signal being at a first logic stage; a first and a second pull-down transistors having their source/drain paths connected in series between the intermediate output node and a common potential, and having their gates connected to the input signal, their source/drain path being conductive responsive to the input signal being at a second logic state; an invertor having its input connected to the intermediate output node, to produce an output signal; a feedback transistor having its gate connected to the output signal, and its source/drain path connected in series between a second reference voltage and the series connection between the first and second pull-down transistors, its source/drain path being conductive responsive to the logic state of the output signal; and wherein the first reference voltage and the second reference voltage are the same.

Claim 20

An input circuit comprising: a pull-up transistor having its source/drain path connected in series between a first reference voltage and an intermediate output node, and having its gate connected to an input signal, its source/drain path being conductive responsive to the input signal being at a first logic stage; a first and a second pull-down transistors having their source/drain paths connected in series between the intermediate output node and a common potential, and having their gates connected to the input signal, their source/drain path being conductive responsive to the input signal being at a second logic state; an invertor having its input connected to the intermediate output node, to produce an output signal; a feedback transistor having its gate connected to the output signal, and its source/drain path connected in series between a second reference voltage and the series connection between the first and second pull-down transistors, its source/drain path being conductive responsive to the logic state of the output signal; and wherein the first reference voltage and the second reference voltage are the same.

Claim 21

An input circuit comprising: a pull-up transistor having its source/drain path connected in series between a first reference voltage and an intermediate output node, and having its gate connected to an input signal, its source/drain path being conductive responsive to the input signal being at a first logic stage; a first and a second pull-down transistors having their source/drain paths connected in series between the intermediate output node and a common potential, and having their gates connected to the input signal, their source/drain path being conductive responsive to the input signal being at a second logic state; an invertor having its input connected to the intermediate output node, to produce an output signal; a feedback transistor having its gate connected to the output signal, and its source/drain path connected in series between a second reference voltage and the series connection between the first and second pull-down transistors, its source/drain path being conductive responsive to the logic state of the output signal; and wherein the second reference voltage is lower than the first reference voltage.

Claim 22

An input circuit comprising: a pull-up transistor having its source/drain path connected in series between a first reference voltage and an intermediate output node, and having its gate connected to an input signal, its source/drain path being conductive responsive to the input signal being at a first logic stage; a first and a second pull-down transistors having their source/drain paths connected in series between the intermediate output node and a common potential, and having their gates connected to the input signal, their source/drain path being conductive responsive to the input signal being at a second logic state; an invertor having its input connected to the intermediate output node, to produce an output signal; a feedback transistor having its gate connected to the output signal, and its source/drain path connected in series between a second reference voltage and the series connection between the first and second pull-down transistors, its source/drain path being conductive responsive to the logic state of the output signal; and wherein the second reference voltage is lower than the first reference voltage.

Claim 23

An input circuit comprising: a pull-up transistor having its source/drain path connected in series between a first reference voltage and an intermediate output node, and having its gate connected to an input signal, its source/drain path being conductive responsive to the input signal being at a first logic stage; a first and a second pull-down transistors having their source/drain paths connected in series between the intermediate output node and a common potential, and having their gates connected to the input signal, their source/drain path being conductive responsive to the input signal being at a second logic state; an invertor having its input connected to the intermediate output node, to produce an output signal; a feedback transistor having its gate connected to the output signal, and its source/drain path connected in series between a second reference voltage and the series connection between the first and second pull-down transistors, its source/drain path being conductive responsive to the logic state of the output signal; and a second pull-up transistor having its source/drain path connected in series between a voltage supply and the source/drain path of the pull-up transistor, and having its gate connected to a voltage reference generator circuit, its source/drain path being always conductive.

Claim 24

An input circuit comprising: a pull-up transistor having its source/drain path connected in series between a first reference voltage and an intermediate output node, and having its gate connected to an input signal, its source/drain path being conductive responsive to the input signal being at a first logic stage; a first and a second pull-down transistors having their source/drain paths connected in series between the intermediate output node and a common potential, and having their gates connected to the input signal, their source/drain path being conductive responsive to the input signal being at a second logic state; an invertor having its input connected to the intermediate output node, to produce an output signal; a feedback transistor having its gate connected to the output signal, and its source/drain path connected in series between a second reference voltage and the series connection between the first and second pull-down transistors, its source/drain path being conductive responsive to the logic state of the output signal; and a second pull-up transistor having its source/drain path connected in series between a voltage supply and the source/drain path of the pull-up transistor, and having its gate connected to a voltage reference generator circuit, its source/drain path being always conductive.

Claim 25

The circuit of claim 17 further comprising: a third pull-up transistor having its source/drain path connected between the voltage supply and the input of the inverter, and having its gate connected to the output.

Claim 26

The circuit of claim 17 further comprising: a third pull-up transistor having its source/drain path connected between the second reference voltage and the input of the inverter, and having its gate connected to the output.

Claim 27

An input circuit comprising: a pull-up transistor having its source/drain path connected in series between a first reference voltage and an intermediate output node, and having its gate connected to an input signal, its source/drain path being conductive responsive to the input signal being at a first logic stage; a first and a second pull-down transistors having their source/drain paths connected in series between the intermediate output node and a common potential, and having their gates connected to the input signal, their source/drain path being conductive responsive to the input signal being at a second logic state; an invertor having its input connected to the intermediate output node, to produce an output signal; a feedback transistor having its gate connected to the output signal, and its source/drain path connected in series between a second reference voltage and the series connection between the first and second pull-down transistors, its source/drain path being conductive responsive to the logic state of the output signal; and a second pull-up transistor having its source/drain path connected in series between a voltage supply and the source/drain path of the pull-up transistor, and having its gate connected to the voltage supply, its source/drain path always being conductive.

Claim 28

An input circuit comprising: a pull-up transistor having its source/drain path connected in series between a first reference voltage and an intermediate output node, and having its gate connected to an input signal, its source/drain path being conductive responsive to the input signal being at a first logic stage; a first and a second pull-down transistors having their source/drain paths connected in series between the intermediate output node and a common potential, and having their gates connected to the input signal, their source/drain path being conductive responsive to the input signal being at a second logic state; an invertor having its input connected to the intermediate output node, to produce an output signal; a feedback transistor having its gate connected to the output signal, and its source/drain path connected in series between a second reference voltage and the series connection between the first and second pull-down transistors, its source/drain path being conductive responsive to the logic state of the output signal; and a second pull-up transistor having its source/drain path connected in series between a voltage supply and the source/drain path of the pull-up transistor, and having its gate connected to the voltage supply, its source/drain path always being conductive.

Claim 29

The circuit of claim 20 further comprising: a third pull-up transistor having its source/drain path connected between the voltage supply and the input of the inverter, and having its gate connected to the output.

Claim 30

The circuit of claim 20 further comprising: a third pull-up transistor having its source/drain path connected between the second reference voltage and the input of the inverter, and having its gate connected to the output.

Claim 31

A CMOS input buffer comprising: a pull-up transistor having its source/drain path connected in series between a voltage supply and a first reference voltage, and having its gate connected to a reference voltage generator circuit; a CMOS inverter having the source/drain paths of its p-channel transistor and its n-channel transistor connected in series between the first reference voltage and a node, and having the gates of its p-channel transistor and its n-channel transistor connected to the input signal; a pull-down transistor having its source/drain path connected in series between a common potential and the node; an inverter having its input connected to the source/drain path of the CMOS inverter, and having an output; a feedback transistor having its gate connected to the output, and its source/drain path connected in series between a second reference voltage and the node; and wherein the relative sizes of the p-channel transistor and the n-channel transistor of the CMOS inverter, and the pull-down transistor and the feedback transistor cause the CMOS inverter to have a low level trip point and a high level trip point.

Claim 32

A CMOS input buffer comprising: a pull-up transistor having its source/drain path connected in series between a voltage supply and a first reference voltage, and having its gate connected to a reference voltage generator circuit; a CMOS inverter having the source/drain paths of its p-channel transistor and its n-channel transistor connected in series between the first reference voltage and a node, and having the gates of its p-channel transistor and its n-channel transistor connected to the input signal; a pull-down transistor having its source/drain path connected in series between a common potential and the node; an inverter having its input connected to the source/drain path of the CMOS inverter, and having an output; a feedback transistor having its gate connected to the output, and its source/drain path connected in series between a second reference voltage and the node; and wherein the relative sizes of the p-channel transistor and the n-channel transistor of the CMOS inverter, and the pull-down transistor and the feedback transistor cause the CMOS inverter to have a low level trip point and a high level trip point.

Claim 33

The CMOS input buffer of claim 23 wherein the first reference voltage and the second reference voltage are the same.

Claim 34

The CMOS input buffer of claim 23 wherein the second reference voltage is higher than the first reference voltage.

Claim 35

The CMOS input buffer of claim 23 wherein the second reference voltage is lower than the first reference voltage.

Claim 36

The CMOS input buffer of claim 23 further comprising: a second pull-up transistor having its source/drain path connected in series between the voltage supply and the input of the inverter and having its gate connected to the output.

Claim 37

The CMOS input buffer of claim 23 further comprising: a second pull-up transistor having its source/drain path connected in series between the second reference voltage and the input of the inverter and having its gate connected to the input.