Semiconductor device having an interposing layer between an electrode and a connection electrode

Claim 2

A semiconductor device comprising: a first electrode region formed on one major surface of a substrate of first conductivity type and having a second conductivity type opposite to the first conductivity type; a second electrode region of the first conductivity type formed in the first electrode region by impurity diffusion, the second electrode region partially exposed through a surface of the first electrode region; a third electrode region of the second conductivity type formed in the second electrode region by impurity diffusion, the third electrode region partially exposed through a surface of the second electrode region; a gate insulating film formed on the first electrode region, the gate insulating film having an opening for exposing the second and third electrode regions; a gate electrode formed on the gate insulating film partially over the first electrode region; an insulating interlayer formed in a manner to cover the gate electrode; a metal electrode film formed as a connection electrode over the gate electrode with the insulating interlayer exclusively interposed between the gate electrode and the metal electrode film and the metal electrode film extending over the second and third electrode regions the metal electrode film ohmically connected to the second electrode region; and an interposing layer comprising conductive layers for electrical connection formed exclusively on the third electrode region and interposing between the metal electrode film and the third electrode region, and interposing layer being so formed that the metal electrode film is not electrically connected directly to the third electrode region.

Claim 3

The semiconductor device according to claim 1, wherein the interposing layer is formed of poly-Si.

Claim 4

The semiconductor device according to claim 1, wherein the interposing layer is formed of a metal thin film having a resistance.

Claim 5

The semiconductor device according to claim 1, wherein the interposing layer is formed of single crystalline silicon.

Claim 6

The semiconductor device according to claim 1, wherein an insulating wall is so formed as to partially cover the second and third electrode regions and the interposing layer is formed over the third electrode region at a location defined between the insulating wall and the insulating interlayer.

Claim 7

The semiconductor device according to claim 5, wherein the interposing layer is formed of P type poly-Si having a high impurity concentrtion.

Claim 8

The semiconductor device according to claim 5, wherein the interposing layer comprises very thin insulation.

Claim 9

A semiconductor device comprising: a first electrode region formed on one major surface of a semiconductor substrate of first conductivity type and having a second conductivity type opposite to the first conductivity type; a second electrode region of the first conductivity type formed in the first electrode region by impurity diffusion, the second electrode region partially exposed through a surface of the first electrode region; a third electrode region of the second conductivity type formed in the second electrode region by impurity diffusion, the third electrode region partially exposed through a surface of the second electrode region; a gate insulating film formed on the first electrode region, the gate insulating film having an opening for exposing the second and third electrode regions; a gate electrode formed on the gate insulating film partially over the first electrode region; an insulating interlayer formed over the gate electrode to cover the gate electrode; an emitter metal electrode film formed on the third electrode region, the emitter metal electrode film electrically connected to the third electrode region only; a base metal electrode film formed on the second electrode region to be electrically connected to the second electrode region only; and a resistor connected between the emitter metal electrode and the base metal electrode film, the resistor acting as a negative feedback resistor.

Claim 10

A semiconductor device comprising: a first electrode region formed on one major surface of a semiconductor substrate of first conductivity type and having a second conductivity type opposite to the first conductivity type; a second electrode region of the first conductivity type formed in the first electrode region by impurity diffusion, the second electrode region partially exposed through a surface of the first electrode region; a third electrode region of the second conductivity type formed in the second electrode region by impurity diffusion, the third electrode region partially exposed through a surface of the second electrode region; a gate insulating film formed on the first electrode region, the gate insulating film having an opening for exposing the second and third electrode regions; a gate electrode formed on the gate insulating film partially over the first electrode region; an insulating interlayer formed over the gate electrode to cover the gate electrode; an emitter metal electrode film formed on the third electrode region, the emitter metal electrode film electrically connected to the third electrode region only; a base metal electrode film formed on the second electrode region to be electrically connected to the second electrode region only; and a resistor connected between the emitter metal electrode and the base metal electrode film, the resistor acting as a negative feedback resistor.

Claim 11

The semiconductor device according to claim 8, wherein a plurality of resistors are connected between the emitter metal electrode films and the base metal electrode film.

Claim 12

The semiconductor device according to claim 8, wherein the resistors act as a juction diode element.

Claim 13

A lateral IGBT comprising: a semiconductor substrate of a first conductivity type having a major surface; a first electrode region composed of two electrode regions of a second conductivity type formed in the semiconductor substrate in a manner to be exposed on the major surface of the semiconductor substrate, one of the two electrode regions having a different impurity concentration than the other electrode region; a second electrode region of the first conductivity type formed in a manner to be exposed on the major surface of the semiconductor substrate, the second electrode region being formed ina spaced-apart relation to the first electrode region to define a channel forming region in the semiconductor substrate between the first and second electrode regions; a collector region of the first conductivity type formed in the first electrode region which has higher impurity concentration; a third electrode region of the second conductivity type formed in the second electrode region; a gate insulating film formed over the first, second and third electrode regions to at least partially cover the first, second and third electrode regions; a gate electrode formed of a conductive layer formed on the gate insulating film over the channel forming region; insulating interlayers formed on the gate electrode to cover the gate electrode; a first metal electrode film formed over the second and third electrode regions in ohmic contact with the second electrode region; seocnd metal electrode film formed on the collector region in a manner to be in ohmic contact with the collector region, the second metal electrode film electrically isolated from the first metal electrode film; and an interposing layer formed of a conductive layer for electrical connection, the interposing layer being interposed between the first metal electrode film and the third electrode region and the interposing layer located such that the first metal electrode film is not in direct contact with the third electrode region.

Claim 14

A lateral IGBT comprising: a semiconductor substrate of a first conductivity type having a major surface; a first electrode region composed of two electrode regions of a second conductivity type formed in the semiconductor substrate in a manner to be exposed on the major surface of the semiconductor substrate, one of the two electrode regions having a different impurity concentration than the other electrode region; a second electrode region of the first conductivity type formed in a manner to be exposed on the major surface of the semiconductor substrate, the second electrode region being formed ina spaced-apart relation to the first electrode region to define a channel forming region in the semiconductor substrate between the first and second electrode regions; a collector region of the first conductivity type formed in the first electrode region which has higher impurity concentration; a third electrode region of the second conductivity type formed in the second electrode region; a gate insulating film formed over the first, second and third electrode regions to at least partially cover the first, second and third electrode regions; a gate electrode formed of a conductive layer formed on the gate insulating film over the channel forming region; insulating interlayers formed on the gate electrode to cover the gate electrode; a first metal electrode film formed over the second and third electrode regions in ohmic contact with the second electrode region; seocnd metal electrode film formed on the collector region in a manner to be in ohmic contact with the collector region, the second metal electrode film electrically isolated from the first metal electrode film; and an interposing layer formed of a conductive layer for electrical connection, the interposing layer being interposed between the first metal electrode film and the third electrode region and the interposing layer located such that the first metal electrode film is not in direct contact with the third electrode region.

Claim 15

The DMOS according to claim 1, wherein it is replaced by a lateral DMOS FET.

Claim 16

The semiconductor device according to claim 1 which is a vertical DMOS FET.

Claim 17

The semiconductor device according to claim 3 wherein the connection between the interposing layer and the third electrode region is non-ohmic.

Claim 18

A semiconductor device comprising: a first electrode region formed on one major surface of a substrate of first conductivity type and having a second conductivity type opposite to the first conductivity type; a second electrode region of the first conductivity type formed in the first electrode region by impurity diffusion, the second electrode region partially exposed through a surface of the first electrode region; a third electrode region of the second conductivity type formed in the second electrode region by impurity diffusion, the third electrode region partially exposed through a surface of the second electrode region; a gate insulating film formed on the first electrode region, the gate insulating film having an opening for exposing the second the third electrode regions; a gate electrode formed on the gate insulating film partially over the first electrode region; an insulating interlayer formed in a a manner to cover the gate electrode; a metal electrode film formed as a connection electrode over the gate electrode with the insulating interlayer exclusively interposed between the gate electrode and the metal electrode film and the metal electrode film extending over the second and third electrodes, the metal electrode film ohmically connected to the second electrode region; wherein a non-ohmic junction is formed by lowering an impurity concentration in a surface portion of the third electrode region so that a potential difference is developed across the third electrode layer and the metal electrode film upon the conduction of the device.

Claim 19

A semiconductor device comprising: a first electrode region formed on one major surface of a substrate of first conductivity type and having a second conductivity type opposite to the first conductivity type; a second electrode region of the first conductivity type formed in the first electrode region by impurity diffusion, the second electrode region partially exposed through a surface of the first electrode region; a third electrode region of the second conductivity type formed in the second electrode region by impurity diffusion, the third electrode region partially exposed through a surface of the second electrode region; a gate insulating film formed on the first electrode region, the gate insulating film having an opening for exposing the second the third electrode regions; a gate electrode formed on the gate insulating film partially over the first electrode region; an insulating interlayer formed in a a manner to cover the gate electrode; a metal electrode film formed as a connection electrode over the gate electrode with the insulating interlayer exclusively interposed between the gate electrode and the metal electrode film and the metal electrode film extending over the second and third electrodes, the metal electrode film ohmically connected to the second electrode region; wherein a non-ohmic junction is formed by lowering an impurity concentration in a surface portion of the third electrode region so that a potential difference is developed across the third electrode layer and the metal electrode film upon the conduction of the device.