Vertical field-effect transistor

Abstract

Abstract PURPOSE:To contrive a reduction in series resistance and a reduction in heat resistance by a method wherein the thickness of the semiconductor substrate of a vertical power MOSFET is made thinner than that of an active region. CONSTITUTION:The thickness of an N-type high-impurity concentration substrate 1 of a vertical power MOSFET and the thickness of a low-impurity concentration drain region 2 having an N-type epitaxial layer are respectively formed in 3 mum and 8 mum. The thicknesses of P-type base regions 3 and N-type source regions 4 are respectively formed in 2 mum and 0.5 mum. Moreover, the thicknesses of gate oxide films 5, poly Si gate electrodes 6 and protective insulating films 7 are respectively formed in 20 nm, 0.3 mum and 0.6 mum and a source electrode 8 consists of an Al film of a thickness of 3 mum. Moreover, a drain electrode 9 is formed in a thickness of 2 mum. That is, the thickness of the substrate 1 is formed thinner compared to that of the drain region 2.

Inventors

• 👤 Isao Yoshida
• 👤 功 吉田
• 👤 Shigeo Otaka
• 👤 成雄 大高
• 👤 Masatoshi Morikawa
• 👤 正敏 森川

Bibliographic Details