US5032533A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a nonvolatile memory cell with field-plate switch
Assignee: Texas Instruments Inc
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Filing: 1989-12-04
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Granted: 1991-07-16
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Expires: 2009-12-04
Abstract
Abstract An array of nonvolatile memory cells are formed at a face of a semiconductor body, the cells including source regions and including drain regions that are part of a common drain column conductor. Each cell has first and second sub-channel regions between source and drain. The conductivity of the first sub-channel regions of each cell is controlled by a field-plate conductor formed over and insulated from the first sub-channel region. The conductivity of each of the second sub-channel regions is controlled by a floating-gate conductor formed over and insulated from the second sub-channel region. A row line, including control gates, is located above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor switch provided isolation of the cells during programming.
Inventors
- 👤 Manzur Gill
- 👤 Sebastiano D'Arrigo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:47
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
292 words
A method for fabricating at least first and second electrically erasable and programmable memory cells at a face of a semiconductor layer having a first conductivity type, comprising the steps of: selectively doping said semiconductor layer with a dopant of a second conductivity type opposite said first conductivity type to create a source region of said first cell, a drain column diffusion including drain regions of said first and second cells, said drain region of said first cell spaced from the source region of said first cell by first and second sub-channel regions of said first cell, and a source region of said second cell spaced from said drain region of said second cell by first and second sub-channel regions of said second cell and spaced from said source region of said first cell; differentially growing insulator regions over said face to create thermal insulator regions over said source and drain regions and a first insulator layer in between and on either side of said source and drain regions; selectively etching through a second insulator layer, a first conductive layer underlying said second insulator layer, and said first insulator layer underlying said first conductive layer to define a field-plate conductor and a field-plate insulator over said drain regions and said first sub-channel regions adjacent said drain regions; forming window areas on said face adjacent to said respective source regions and forming a thin window insulator layer over each said window area and forming a third insulator layer over said respective second sub-channel regions adjacent said source regions; and forming first and second floating-gate conductors each formed over a respective source region, window insulator and said second sub-channel region and forming a control-gate conductor over, and insulated from, said field-plate and floating-gate conductors.
Claim 2
Independent Claim
292 words
A method for fabricating at least first and second electrically erasable and programmable memory cells at a face of a semiconductor layer having a first conductivity type, comprising the steps of: selectively doping said semiconductor layer with a dopant of a second conductivity type opposite said first conductivity type to create a source region of said first cell, a drain column diffusion including drain regions of said first and second cells, said drain region of said first cell spaced from the source region of said first cell by first and second sub-channel regions of said first cell, and a source region of said second cell spaced from said drain region of said second cell by first and second sub-channel regions of said second cell and spaced from said source region of said first cell; differentially growing insulator regions over said face to create thermal insulator regions over said source and drain regions and a first insulator layer in between and on either side of said source and drain regions; selectively etching through a second insulator layer, a first conductive layer underlying said second insulator layer, and said first insulator layer underlying said first conductive layer to define a field-plate conductor and a field-plate insulator over said drain regions and said first sub-channel regions adjacent said drain regions; forming window areas on said face adjacent to said respective source regions and forming a thin window insulator layer over each said window area and forming a third insulator layer over said respective second sub-channel regions adjacent said source regions; and forming first and second floating-gate conductors each formed over a respective source region, window insulator and said second sub-channel region and forming a control-gate conductor over, and insulated from, said field-plate and floating-gate conductors.
Claim 3
Dependent Claim
60 words
The method of claim 1, and further comprising the steps of: after said step of forming said third insulator layer; forming floating-gate conductor strips over the face; forming an oxide layer on said floating-gate conductor strips; forming a nitride layer on said oxide layer; and forming a second oxide layer on said nitride layer to create a three-insulator oxide-nitride-oxide layer.
Claim 4
Dependent Claim
104 words
The method of claim 1, wherein said first and second cells are formed with a row of an array of rows and columns of such cells, the method further comprising: selectively etching said first conductive layer to form spaced-apart field-plate column lines; forming a floating-gate conductive layer; forming spaced-apart floating-gate conductor strips from said floating-gate conductive layer; forming a control-gate layer; and forming spaced-apart row lines, including said control-gate conductors, from said control-gate layer for each said row of cells, at the same time defining a plurality of said floating-gate conductors having edges that are aligned with the edges of said row line conductors.
Claim 5
Dependent Claim
17 words
The method of claim 1, and further including the step of implanting dopant through said window areas.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |