Control circuit for a semiconductor memory device and semiconductor memory system

Claim 2

A control circuit for a semiconductor memory device comprising: a RAS input terminal for receiving a row-address strobe (RAS) signal having an active period with a predetermined starting point; a row control circuit including a row-address control circuit for said semiconductor memory device; and first timer means for receiving said RAS signal, for generating a row control signal, delayed by a first delay period, such that said row control signal is activated in response to said predetermined starting point of said active period, for each length of said active period when said active period is shorter than said first delay period, and for supplying said row control signal to said row control circuit.

Claim 3

A control circuit for a semiconductor memory device according to claim 1, further comprising a column control circuit including: a column address control circuit for the semiconductor memory; and second timer means for receiving said RAS signal, for generating a first column control signal, delayed by a second delay period, such that said first column control signal becomes active in response to said predetermined starting point of said active period, for each length of said active period when said active period is shorter than said second delay period, and for supplying said first column control signal to said column control circuit.

Claim 4

A control circuit for a semiconductor memory device according to claim 2, further comprising: third timer means for receiving the RAS signal, for generating a second column control signal, delayed by a third delay period, such that said second column control signal becomes active in response to said predetermined starting point of said active period, for each length of said active period when said active period is shorter than said third delay period, and for supplying said second column control signal to said column control circuit.

Claim 5

A control circuit for a semiconductor memory device according to claim 3, wherein said RAS signal is a pulse signal having a width of less than 80 nsec, and said third timer means is activated for said third delay period after said third timer means responds to said RAS signal.

Claim 6

A control circuit for a semiconductor memory device according to claim 3, wherein said third timer means comprises: a third inverter circuit for receiving a word-line driving signal: a third delay circuit, connected to the output of said third inverter circuit, for delaying the word-line driving signal by said third delay period; and a third 2-input NAND gate circuit having a first input for receiving the word-line driving signal, and a second input connected to the output of said third delay circuit.

Claim 7

A control circuit for a semiconductor memory device according to claim 3, wherein said first delay period is longer than said third active delay period, and said third active delay period is longer that said second active delay period.

Claim 8

A control circuit for a semiconductor memory device according to claim 3, wherein said third timer means supplies said delayed RAS signal to a column decoder incorporated in said column control circuit.

Claim 9

A control circuit for a semiconductor memory device according to claim 2, wherein said second timer means comprises: a second inverter circuit for receiving a word-line driving signal: a second delay circuit, connected to the output of said first inverter circuit, for delaying the word-line driving signal by said second delay period; and a second 2-input NAND gate circuit having a first input for receiving the word=line driving signal, and a second input connected to the output of said second delay circuit.

Claim 10

A control circuit for a semiconductor memory device according to claim 2, wherein said RAS signal is a pulse signal having a width of less than 80 nsec, and said second timer means is activated for said second delay period after said second timer means responds to said RAS signal.

Claim 11

A control circuit for a semiconductor memory device according to claim 2, wherein said first delay period is longer than said second delay period.

Claim 12

A control circuit for a semiconductor memory device according to claim 1, wherein said first timer means comprises: a first inverter circuit for receiving a word-line driving signal: a first delay circuit, connected to the output of said first inverter circuit, for delaying the word-line driving signal by said first delay period; and a first 2-input NAND gate circuit having a first input for receiving the word-line driving signal, and a second input connected to the output of said first delay circuit.

Claim 13

A control circuit for a semiconductor memory device according to claim 1, wherein said RAS signal is a pulse signal having a width of less than 80 nsec, and said first timer means is activated for said first delay period after said first timer means responds to said RAS signal.

Claim 14

A semiconductor memory device system comprising: a semiconductor chip including: a RAS input terminal for receiving a row-address strobe (RAS) signal having an active period with a predetermined starting point; and first timer means for receiving said RAS signal, and for generating a row control signal, delayed by a first delay period, such that said row control signal becomes active in response to the predetermined starting point, for each length of said active period when said active period is shorter than said first delay period; and a semiconductor memory device including: a row control circuit; a column control circuit; a first input terminal for receiving said row control signal from said first timer means and for supplying said row control signal to said row control circuit; and a second input terminal for receiving said RAS signal and for supplying said RAS signal to said column control circuit.

Claim 15

A semiconductor memory device system comprising: a semiconductor chip including: a RAS input terminal for receiving a row-address strobe (RAS) signal having an active period with a predetermined starting point; and first timer means for receiving said RAS signal, and for generating a row control signal, delayed by a first delay period, such that said row control signal becomes active in response to the predetermined starting point, for each length of said active period when said active period is shorter than said first delay period; and a semiconductor memory device including: a row control circuit; a column control circuit; a first input terminal for receiving said row control signal from said first timer means and for supplying said row control signal to said row control circuit; and a second input terminal for receiving said RAS signal and for supplying said RAS signal to said column control circuit.

Claim 16

A semiconductor memory device system according to claim 13, wherein said first timer means comprises: a first inverter circuit for receiving a word-line driving signal; a first delay circuit, connected to the output of said first inverter circuit, for delaying the word-line driving signal by said first delay period; and a 2-input NAND gate circuit having a first input for receiving said word-line driving signal, and a second input, connected to the output of said first delay circuit.

Claim 17

A semiconductor memory device system according to claim 13, wherein said RAS signal is a pulse signal having a width of less than 80 nsec, and said first timer means is activated for said first delay period after said first timer means responds to said RAS signal.

Claim 18

A semiconductor memory device system comprising: a semiconductor chip including: a RAS input terminal for receiving a row-address strobe (RAS), signal having an active period with a predetermined starting point: first timer means for receiving said RAS signal, and for generating a row control signal delayed by a first delay period, such that said row control signal becomes active in response to the predetermined starting point, for each length of the active period when said active period is shorter than said first active period; and second timer means for receiving said RAS signal, and for generating a column control signal delayed by a second delay period, such that said column control signal becomes active in response to said predetermined starting point, for each length of said active period when said active period is shorter than said second delay period; and a semiconductor memory device including: a row control circuit; a column control circuit; a first input terminal for receiving said row control signal from said first timer means and for supplying said row control signal to said row control circuit; and a second input terminal for receiving said column control signal from said second timer means and for supplying said RAS signal to said column control circuit.

Claim 19

A semiconductor memory device system comprising: a semiconductor chip including: a RAS input terminal for receiving a row-address strobe (RAS), signal having an active period with a predetermined starting point: first timer means for receiving said RAS signal, and for generating a row control signal delayed by a first delay period, such that said row control signal becomes active in response to the predetermined starting point, for each length of the active period when said active period is shorter than said first active period; and second timer means for receiving said RAS signal, and for generating a column control signal delayed by a second delay period, such that said column control signal becomes active in response to said predetermined starting point, for each length of said active period when said active period is shorter than said second delay period; and a semiconductor memory device including: a row control circuit; a column control circuit; a first input terminal for receiving said row control signal from said first timer means and for supplying said row control signal to said row control circuit; and a second input terminal for receiving said column control signal from said second timer means and for supplying said RAS signal to said column control circuit.

Claim 20

A semiconductor memory device according to claim 16, wherein said first delay period is longer than said second delay period.

Claim 21

A semiconductor memory device system according to claim 16, wherein said second timer means comprises: a second inverter circuit for receiving a word-line driving signal; a second delay circuit, connected to the output of said second inverter circuit, for delaying said word-line driving signal by said second delay period; and a second 2-input NAND gate circuit having a first input for receiving said word-line driving signal, and a second input, connected to the output of said second delay circuit.

Claim 22

A semiconductor memory device system according to claim 16, wherein said RAS signal is a pulse signal having a width of less than 80 nsec, and said second timer means is activated for said second delay period after said second timer means responds to said RAS signal.

Claim 23

A semiconductor memory device system comprising: a semiconductor chip including: a RAS input terminal for receiving a row-address strobe (RAS) signal having an active period with a predetermined starting point: first timer means for receiving said RAS signal, and for generating a row control signal delayed by a first delay period, such that said row control signal becomes active in response to said predetermined starting point, for each length of said active period when said active period is shorter than said first delay period; second timer means for receiving said RAS signal, and for generating a column control signal delayed by a second delay period, such that said column control signal becomes active in response to said predetermined starting point, for each length of said active period when said active period is shorter than said second delay period; and third timer means for receiving said RAS signal, and for generating a second column control signal delayed by a third delay period, such that said second column control signal becomes active in response to said predetermined starting point, for each length of said active period when said active period is shorter than said third delay period; and semiconductor memory device including: a row control circuit; a column control circuit; a first input terminal for receiving said row control signal from said first timer means and for supplying said row control signal to said row control circuit, a second input terminal for receiving said first column control signal from said second timer means and for supplying said first column control signal to said column control circuit, and a third input terminal for receiving said second column control signal from said third timer means and for supplying said second column control signal to said column control circuit.

Claim 24

A semiconductor memory device system comprising: a semiconductor chip including: a RAS input terminal for receiving a row-address strobe (RAS) signal having an active period with a predetermined starting point: first timer means for receiving said RAS signal, and for generating a row control signal delayed by a first delay period, such that said row control signal becomes active in response to said predetermined starting point, for each length of said active period when said active period is shorter than said first delay period; second timer means for receiving said RAS signal, and for generating a column control signal delayed by a second delay period, such that said column control signal becomes active in response to said predetermined starting point, for each length of said active period when said active period is shorter than said second delay period; and third timer means for receiving said RAS signal, and for generating a second column control signal delayed by a third delay period, such that said second column control signal becomes active in response to said predetermined starting point, for each length of said active period when said active period is shorter than said third delay period; and semiconductor memory device including: a row control circuit; a column control circuit; a first input terminal for receiving said row control signal from said first timer means and for supplying said row control signal to said row control circuit, a second input terminal for receiving said first column control signal from said second timer means and for supplying said first column control signal to said column control circuit, and a third input terminal for receiving said second column control signal from said third timer means and for supplying said second column control signal to said column control circuit.

Claim 25

A semiconductor memory device system according to claim 20, wherein said third timer means comprises: a third inverter circuit for receiving a word-line driving signal; a third delay circuit, connected to the output of said third inverter circuit, for delaying said word-line driving signal by said third active delay period; and a third 2-input NAND gate circuit having a first input for receiving said word-line driving signal, and a second input, connected to the output of said third delay circuit.

Claim 26

A semiconductor memory device system according to claim 20, wherein said third timer means supplies said delayed RAS signal to a column-address decoder in said column control circuit.

Claim 27

A semiconductor memory device according to claim 20, wherein said first delay period is longer than said third delay period, and said third delay period is longer than said second delay period.

Claim 28

A semiconductor memory device system according to claim 20, wherein said RAS signal is a pulse signal having a width of less than 80 nsec, and said third timer means is activated for said third delay period time after said third timer means responds to said RAS signal.

Claim 29

A semiconductor memory device system according to claim 20, wherein said second timer means comprises: a second inverter circuit for receiving a word-line driving signal; a second delay circuit, connected to the output of said second inverter circuit, for delaying the word-line driving signal by said second delay period; and a second 2-input NAND gate circuit having a first input for receiving the word-line driving signal, and a second input, connected to the output of said second delay circuit.

Claim 30

A semiconductor memory device according to claim 20, wherein said first delay period is longer than said second delay period.

Claim 31

A control circuit for a semiconductor memory device comprising: a RAS input terminal for receiving a row-address strobe (RAS) signal having an active period with a predetermined starting point; a row control circuit, including a row-address control circuit; a column control circuit, connected to the RAS input terminal, including a column-address control circuit; and a timer means for receiving the RAS signal, and for generating a row control signal delayed by a given active period, such that the row control signal becomes active in response to the predetermined starting point of the active period, for each length of the active period, when the active period is shorter than the given active period, and for supplying said row control signal to the row control circuit.

Claim 32

A control circuit for a semiconductor memory device comprising: a RAS input terminal for receiving a row-address strobe (RAS) signal having an active period with a predetermined starting point; a row control circuit, including a row-address control circuit; a column control circuit, connected to the RAS input terminal, including a column-address control circuit; and a timer means for receiving the RAS signal, and for generating a row control signal delayed by a given active period, such that the row control signal becomes active in response to the predetermined starting point of the active period, for each length of the active period, when the active period is shorter than the given active period, and for supplying said row control signal to the row control circuit.