Dynamic random access memory device having an improved timing arrangement

Claim 2

A dynamic random access memory device comprising: (a) a plurality of pairs of bit lines (BL, /BL); (b) a plurality of word lines (WL) for applying word signals; (c) a plurality of memory cells, each of said memory cells being connected to a respective bit line and a respective word line, and each of said memory cells comprising a MOS transistor (4) and charge storage means (12); (d) a plurality of sense amplifier circuits (16), each of said sense amplifier circuits comprising a first and a second MOS driver transistor, said first driver transistor being connected between one bit line of a corresponding pair of bit lines and a common potential node, a gate electrode of said first driver transistor being connected to the other bit line of said corresponding pair of bit lines, said second driver transistor being connected between said other bit line of said corresponding pair of bit lines and said common potential node, a gate electrode of said second driver transistor being connected to said one of said corresponding pair of bit lines; (e) an enable MOS transistor (7) connected between said common potential node and a ground node, a gate electrode of said enable transistor receiving an enable signal; (f) a pair of input/output lines (I/O, /I/O); (g) a plurality of pairs of transfer MOS transistors, one transistor of each of said pairs of transfer transistors being connected between one bit line of an associated pair of bit lines and one of said input/output lines, a gate electrode of said one transistor of each of said pairs of transfer transistors receiving a column signal, the other transistor of each of said pairs of transfer transistors being connected between the other bit line of said associated pair of bit lines and the other of said pair of input/output lines, and a gate electrode of said other transistor of each of said pairs of transfer transistors receiving said column signal; (h) an input/output load (13) connected to said pair of input/output lines; and (i) a control circuit receiving an external /RAS signal and generating an internal /RAS signal controlling at least production of said word signals and said enable signals, a reset timing of said internal /RAS signal being delayed with respect to a reset timing of said external /RAS signal, whereby a time when the MOS transistor of a selected memory cell and said enable MOS transistor are made nonconductive is delayed beyond a time when a selected one of said pairs of transfer MOS transistors are made nonconductive.

Claim 3

The dynamic random access memory device according to claim 1, wherein said input/output load comprises first and second input/output load MOS transistors, said first transistor being connected between one of said input/output lines and a supply potential node, and said second transistor being connected between the other of said input/output lines and said supply potential node.

Claim 4

The dynamic random access memory device according to claim 1, wherein said control circuit comprises an even number of serially coupled inverters to a first input of which said external /RAS signal is applied, a delay stage to an input of which a final output of said even number of inverters is applied, a NAND gate to one input of which is applied an output of said delay stage and to another input of which is applied to said final output of said serially coupled inverters, and an inverter to an input of which is applied an output of said NAND gate, said internal /RAS signal being present at an output of said inverter.

Claim 5

The dynamic random access memory device according to claim 1, wherein said control circuit comprises a delay stage to an input of which is applied said external /RAS signal, a NAND gate to one input of which is applied an output of said delay stage and to another input of which is applied said external /RAS signal, and an inverter to an input of which is applied an output of said NAND gate, said internal /RAS signal being present at an output of said inverter.

Claim 6

The dynamic random access memory device according to claim 4, wherein said delay stage comprises an even number of inverters.

Claim 7

The dynamic random access memory device according to claim 1, wherein each of said sense amplifier circuits comprises first and second load MOS transistors.

Claim 8

The dynamic random access memory device according to claim 6, wherein said first and second driver MOS transistors are of the N type and said first and second load MOS transistors are of the P type, said first load MOS transistor is connected between one bit line of said corresponding pair of bit lines and a second common potential node, a gate electrode of said first load transistor is connected to the other bit line of said corresponding pair of bit lines, said second load MOS transistor is connected between said other bit line of said corresponding pair of bit lines and said second common node, and a gate electrode of said second load transistor is connected to said one bit line of said corresponding pair of bit lines.

Claim 9

The dynamic random access memory device according to claim 7, further comprising a second enable MOS transistor (1) connected between said second common potential node and a supply potential node.

Claim 10

The dynamic random access memory device according to claim 8, wherein said second enable MOS transistor is of the P type, and a gate electrode of said second enable MOS transistor receives a second enable signal complementary to said first enable signal.

Claim 11

The dynamic random access memory device according to claim 8, further comprising a plurality of equalizer circuits, each of said equalizer circuits being connected between a respective pair of said bit lines.

Claim 12

The dynamic random access memory device according to claim 10, wherein each of said equalizer circuits comprises an MOS transistor.

Claim 13

A dynamic random access memory device comprising: (a) a plurality of pairs of bit lines (BL,/BL); (b) a plurality of word lines (WL) for applying word signals; (c) a plurality of memory cells, each of said memory cells being connected to a respective bit line and a respective word line, and each of said memory cells comprising a MOS transistor (4) and charge storage means (12). (d) a plurality of sense amplifier circuits (16), each of said sense amplifier circuits comprising a first and a second N-type MOS transistor, said first driver transistor being connected between one bit line of a respective pair of said bit lines and a first common potential node, a gate electrode of said first driver transistor being connected to the other bit line of said respective pair of bit lines, said second driver transistor being connected between said other bit line and said first common node, a gate electrode of said second driver transistor being connected to said one bit line, said first load transistor being connected between said one bit line of said respective pair of bit lines and a second common potential node, a gate electrode of said first load transistor being connected to said other bit line of said respective pair of bit lines, said second load transistor being connected between said other bit line of said respective pair of bit lines and said second common potential node, a gate electrode of said second load transistor being connected to said one bit line of said respective pair of bit lines; (e) a first enable N-type MOS transistor (7) connected between said first common potential node and a ground node, a gate electrode of said first enable transistor receiving a first enable signal; (f) a second enable P-type MOS transistor (1) connected between said second common potential node and a supply potential node, a gate electrode of said second enable transistor receiving a second enable signal; (g) a plurality of equalizer circuits for equalizing a potential between the bit lines of respective pairs of said bit lines before and after read-out of information from the respective memory cells, each of said equalizer circuits being connected between a respective pair of said bit lines; (h) a pair of input/output lines (I/O, /I/O); (i) a plurality of pairs of transfer N-type MOS transistors, one transistor of each of said pairs of transfer transistors being connected between one bit line of a respective pair of said bit lines and one of said input/output lines, a gate electrode of said one transistor receiving a column signal, the other transistor of each of said pairs of transfer transistors being connected between the other of said bit lines of said respective pair of bit lines and the other of said input/output lines, and a gate electrode of said other transistor of each of said pairs of transfer transistors receiving said column signal; (j) an input/output load (13) connected to said pair of input/output lines; and (k) a control circuit receiving an external /RAS signal and producing an internal /RAS signal controlling at least said column signal, said first and second enable signals, and signals for enabling said equalizer circuits, a reset timing of said internal /RAS signal being delayed with respect to a reset timing of said external /RAS signal, whereby a time when the MOS transistor of said memory cell and a selected enable MOS transistor are made nonconductive is delayed beyond a time when a selected one of said pairs of transfer MOS transistors are made nonconductive.

Claim 14

A dynamic random access memory device comprising: (a) a plurality of pairs of bit lines (BL,/BL); (b) a plurality of word lines (WL) for applying word signals; (c) a plurality of memory cells, each of said memory cells being connected to a respective bit line and a respective word line, and each of said memory cells comprising a MOS transistor (4) and charge storage means (12). (d) a plurality of sense amplifier circuits (16), each of said sense amplifier circuits comprising a first and a second N-type MOS transistor, said first driver transistor being connected between one bit line of a respective pair of said bit lines and a first common potential node, a gate electrode of said first driver transistor being connected to the other bit line of said respective pair of bit lines, said second driver transistor being connected between said other bit line and said first common node, a gate electrode of said second driver transistor being connected to said one bit line, said first load transistor being connected between said one bit line of said respective pair of bit lines and a second common potential node, a gate electrode of said first load transistor being connected to said other bit line of said respective pair of bit lines, said second load transistor being connected between said other bit line of said respective pair of bit lines and said second common potential node, a gate electrode of said second load transistor being connected to said one bit line of said respective pair of bit lines; (e) a first enable N-type MOS transistor (7) connected between said first common potential node and a ground node, a gate electrode of said first enable transistor receiving a first enable signal; (f) a second enable P-type MOS transistor (1) connected between said second common potential node and a supply potential node, a gate electrode of said second enable transistor receiving a second enable signal; (g) a plurality of equalizer circuits for equalizing a potential between the bit lines of respective pairs of said bit lines before and after read-out of information from the respective memory cells, each of said equalizer circuits being connected between a respective pair of said bit lines; (h) a pair of input/output lines (I/O, /I/O); (i) a plurality of pairs of transfer N-type MOS transistors, one transistor of each of said pairs of transfer transistors being connected between one bit line of a respective pair of said bit lines and one of said input/output lines, a gate electrode of said one transistor receiving a column signal, the other transistor of each of said pairs of transfer transistors being connected between the other of said bit lines of said respective pair of bit lines and the other of said input/output lines, and a gate electrode of said other transistor of each of said pairs of transfer transistors receiving said column signal; (j) an input/output load (13) connected to said pair of input/output lines; and (k) a control circuit receiving an external /RAS signal and producing an internal /RAS signal controlling at least said column signal, said first and second enable signals, and signals for enabling said equalizer circuits, a reset timing of said internal /RAS signal being delayed with respect to a reset timing of said external /RAS signal, whereby a time when the MOS transistor of said memory cell and a selected enable MOS transistor are made nonconductive is delayed beyond a time when a selected one of said pairs of transfer MOS transistors are made nonconductive.

Claim 15

The dynamic random access memory device according to claim 12, wherein said equalizer circuits each comprise a MOS transistor connected between a respective pair of said bit lines, a gate electrode of said transistor being receiving a signal controlled by said internal /RAS signal.

Claim 16

The dynamic random access memory device according to claim 12, wherein said input/output load comprises first and second input/output load MOS transistors, said first transistor being connected between one of said input/output lines and a supply potential node, and said second transistor being connected between the other of said input/output lines and said supply potential node.

Claim 17

The dynamic random access memory device according to claim 12, wherein said control circuit comprises an even number of serially coupled inverters to a first input of which said external /RAS signal is applied, a delay stage to an input of which a final output of said even number of inverters is applied, a NAND gate to one input of which is applied an output of said delay stage and to another input of which is applied said final output of said serially coupled inverters, and an inverter to an input of which is applied an output of said NAND gate, said internal /RAS signal being present at an output of said inverter.

Claim 18

The dynamic random access memory device according to claim 12, wherein said control circuit comprises a delay stage to an input of which is applied said external /RAS signal, a NAND gate to one input of which is applied an output of said delay stage and to another input of which is applied said external /RAS signal, and an inverter to an input of which is applied an output of said NAND gate, said internal /RAS signal being present at an output of said inverter.

Claim 19

The dynamic random access memory device according to claim 16, wherein said delay stage comprises an even number of inverters.