Semiconductor dynamic memory

Claim 2

A semiconductor dynamic memory comprising a plurality of interface circuits including: a row-enable buffer for generating a row enable output signal; a row address buffer, operatively connected to receive the row enable output signal from said row enable buffer; a word decoder operatively connected to said row address buffer; word lines operatively connected to said word decoder; a group of sense amplifiers, operatively connected to said word lines, for generating a sense output signal; a column enable buffer for generating a column enable output signal; a column address buffer, operatively connected to receive the column enable output signal from said column enable buffer, for generating a column address signal in dependence upon the column enable output signal; a column decoder operatively connected to receive the column address signal from said column address buffer and which column address signal selects one of said sense amplifiers; a data buffer operatively connected to receive the sense output signal of the selected sense amplifier; and an output buffer operatively connected to said data buffer, at least one of said interface circuits being reset, so as to be ready to execute the next processing, by a reset signal which is generated by a connected interface circuit which receives an output signal generated by the at least one interface circuit and the reset signal proves that said connected interface circuit has begun its operation.

Claim 3

A semiconductor dynamic memory according to claim 1, wherein said row address buffer and said word decoder generate first and second signals, wherein said row enable buffer is reset by the first signal generated by said row address buffer, and said row address buffer is reset by the second signal generated by said word decoder.

Claim 4

A semiconductor dynamic memory according to claim 1 or 2, wherein said column decoder generates a third signal, wherein both said word decoder and said sense amplifier are reset by the third signal generated by said column decoder.

Claim 5

A semiconductor dynamic memory according to claim 1 or 2, wherein said column decoder generates a fourth signal, wherein said output buffer is reset by the fourth signal generated by said column decoder.

Claim 6

A semiconductor dynamic memory according to claim 1 or 2, wherein said semiconductor dynamic memory is operatively connected to receive an external clock signal having a rising edge and a falling edge, wherein said row-enable buffer commences operation in dependence upon the rising edge or a falling edge of the external clock signal and said column-enable buffer commences operation in dependence upon the falling edge or the rising edge of said external clock signal in dependence upon which edge of the external clock signal initiates operation of said row enable buffer.

Claim 7

A semiconductor dynamic memory according to claim 3, wherein column decoder generates a fourth signal which resets said output buffer.

Claim 8

A semiconductor dynamic memory according to claim 3 wherein said semiconductor dynamic memory is operatively connected to receive an external signal having a rising edge and a falling edge, wherein said row-enable buffer commences operation in dependence upon the rising edge or the falling edge of the external clock signal and said column-enable buffer commences operation in dependence upon the falling edge or the rising edge of said external clock signal in dependence upon which edge of the external clock signal initiates operation of said row-enable buffer.

Claim 9

A semiconductor dynamic memory according to claim 4, wherein said semiconductor dynamic memory is operatively connected to receive an external clock signal having a rising edge and a falling edge, wherein said row-enable buffer commences operation in dependence upon the rising edge or the falling edge of the external clock signal and said column-enable buffer commences operation in dependence upon the falling edge or the rising edge of said external clock signal in dependence upon which edge of the external clock signal initiates operation of said row-enable buffer.

Claim 10

A semiconductor dynamic memory, operatively connectable to receive a row address strobe signal, a column address strobe signal and a write enable signal, comprising: a row-enable buffer, operatively connectable to receive the row address strobe signal, for generating a first signal in dependence upon the row address strobe signal; a row address buffer, operatively connected to said row-enable buffer, for generating a first reset signal and a second signal in dependence upon the first signal, said row-enable buffer being reset by the first reset signal; a word decoder operatively connected to said row address buffer, for generating a second reset signal and a third signal in dependence upon the second signal, said row address buffer being reset by the second reset signal; a sense amplifier, operatively connected to said word decoder, for generating a fourth signal in dependence upon the third signal; a column enable buffer, operatively connectable to receive the column address strobe signal, for generating a fifth signal in dependence upon the column address strobe signal; a column address buffer, operatively connected to said column enable buffer, for generating a third reset signal and a sixth signal in dependence upon the fifth signal, said column enable buffer being reset by the third reset signal; a writing system circuit, operatively connectable to receive the write enable signal, for generating a seventh signal in dependence upon the write enable signal; a column decoder, operatively connected to said word decoder, said sense amplifier, said column address buffer and said writing system circuit, for generating a fourth reset signal and an eighth signal in dependence upon the fourth, sixth and seventh signals, said word decoder, said sense amplifier, said column address buffer and said writing system circuit being reset by said fourth reset signal; a data buffer, operatively connected to said column decoder, for generating a fifth reset signal and a ninth signal in dependence upon the eighth signal, said column decoder being reset by said fifth reset signal; and an output buffer, operatively connected to said data buffer and said column decoder, for generating output data and a sixth reset signal in dependence upon the ninth signal, said data buffer being reset by the sixth reset signal and said output buffer being reset by the eighth signal.

Claim 11

A semiconductor dynamic memory, operatively connectable to receive a row address strobe signal, a column address strobe signal and a write enable signal, comprising: a row-enable buffer, operatively connectable to receive the row address strobe signal, for generating a first signal in dependence upon the row address strobe signal; a row address buffer, operatively connected to said row-enable buffer, for generating a first reset signal and a second signal in dependence upon the first signal, said row-enable buffer being reset by the first reset signal; a word decoder operatively connected to said row address buffer, for generating a second reset signal and a third signal in dependence upon the second signal, said row address buffer being reset by the second reset signal; a sense amplifier, operatively connected to said word decoder, for generating a fourth signal in dependence upon the third signal; a column enable buffer, operatively connectable to receive the column address strobe signal, for generating a fifth signal in dependence upon the column address strobe signal; a column address buffer, operatively connected to said column enable buffer, for generating a third reset signal and a sixth signal in dependence upon the fifth signal, said column enable buffer being reset by the third reset signal; a writing system circuit, operatively connectable to receive the write enable signal, for generating a seventh signal in dependence upon the write enable signal; a column decoder, operatively connected to said word decoder, said sense amplifier, said column address buffer and said writing system circuit, for generating a fourth reset signal and an eighth signal in dependence upon the fourth, sixth and seventh signals, said word decoder, said sense amplifier, said column address buffer and said writing system circuit being reset by said fourth reset signal; a data buffer, operatively connected to said column decoder, for generating a fifth reset signal and a ninth signal in dependence upon the eighth signal, said column decoder being reset by said fifth reset signal; and an output buffer, operatively connected to said data buffer and said column decoder, for generating output data and a sixth reset signal in dependence upon the ninth signal, said data buffer being reset by the sixth reset signal and said output buffer being reset by the eighth signal.

Claim 12

A semiconductor dynamic memory as recited in claim 9, wherein said column strobe signal is the row address strobe signal.

Claim 13

A semiconductor dynamic memory according to claim 9 or 10, wherein said semiconductor dynamic memory is operatively connectable to receive a chip select signal and further comprises a chip select circuit, operatively connectable to receive the chip select signal, for generating a tenth signal in dependence upon the chip select signal, wherein said output buffer generates the output data and the sixth reset signal in dependence upon the ninth signal and the tenth signal.