Asynchronous spatial shift register circuit

Claim 2

An asynchronous spatial iterative circuit, having a first, second, third and fourth input terminals and a first, second, third and fourth output terminals comprising: a three-state memory circuit having three stable internal states and capable of transition from one stable state to another; a logic gate circuit for gating inputs supplied to the first and second input terminals and designating transitions to a first stable state or a second stable state in the memory circuit; and a control circuit means responsive to the internal state of the memory for (1) rendering the gate circuit into conducting state when the memory circuit has finished its transition from the first or second stable state to a third stable state as a result of an input being given to the third input terminal, (2) rendering the gate circuit into non-conducting state when the memory circuit has completed its transition from the third stable state to the first or second stable state, (3) generating a signal indicative of the completion of the control operation (2) at the first output terminal, and (4) invalidating the output signal at the first terminal upon receipt of a response signal at the fourth input terminal; wherein one bit of data in terms of logic 1 and 0 corresponding to the first and second stable states is written, stored and transferred through the second, third and fourth output terminals used to represent in combination the first, second and third stable states.

Claim 3

A shift register comprising a plurality of identical asynchronous spatial iterative circuits each having first to fourth input terminals and first to fourth output terminals and comprising: a three-state memory circuit having three stable internal states and capable of transition from one stable state to another; a logic gate circuit for gating inputs supplied to the first and second input terminals and designating transitions to a first stable state or a second stable state in the memory circuit; and a control circuit means responsive to the internal state of the memory for (1) rendering the gate circuit into conducting state when the memory circuit has finished its transition from the first or second stable state to a third stable state as a result of an input being given to the third input teminal, (2) rendering the gate circuit into nonconducting state when the memory circuit has completed its transition from the third stable state to the first or second stable state, (3) generating a signal indicative of the completion of the control operation (2) at the first output terminal, and (4) invalidating the output signal at the first output terminal upon receipt of a response signal at the fourth input terminal; wherein one bit of data in terms of logic 1 and 0 correspondIng to the first and second stable states is written, stored and transferred through the second, third and fourth output terminals used to represent in combination the first, second and third stable states and wherein the first to fourth input terminals, and the first to fourth output terminals have such signal polarities as to allow the second, third and fourth output terminals and the third input terminal of one of the iterative circuits to be connected to the first, second and fourth input terminals and the first output terminal, respectively, of the following iterative circuit.

Claim 4

A shift register comprising a plurality of identical asynchronous spatial iterative circuits each having first to fourth input terminals and first to fourth output terminals and comprising: a three-state memory circuit having three stable internal states and capable of transition from one stable state to another; a logic gate circuit for gating inputs supplied to the first and second input terminals and designating transitions to a first stable state or a second stable state in the memory circuit; and a control circuit means responsive to the internal state of the memory for (1) rendering the gate circuit into conducting state when the memory circuit has finished its transition from the first or second stable state to a third stable state as a result of an input being given to the third input teminal, (2) rendering the gate circuit into nonconducting state when the memory circuit has completed its transition from the third stable state to the first or second stable state, (3) generating a signal indicative of the completion of the control operation (2) at the first output terminal, and (4) invalidating the output signal at the first output terminal upon receipt of a response signal at the fourth input terminal; wherein one bit of data in terms of logic 1 and 0 correspondIng to the first and second stable states is written, stored and transferred through the second, third and fourth output terminals used to represent in combination the first, second and third stable states and wherein the first to fourth input terminals, and the first to fourth output terminals have such signal polarities as to allow the second, third and fourth output terminals and the third input terminal of one of the iterative circuits to be connected to the first, second and fourth input terminals and the first output terminal, respectively, of the following iterative circuit.

Claim 5

A circuit having three stable states, L1, L0 and L and adapted to assume the stable state indicated by an input signal, said circuit comprising: a. first means responsive to a first externally applied input signal when said circuit is in a quiescent condition for causing said circuit to assume said stable state L , b. second means responsive to said circuit assuming said stable state L for switching said circuit to the set condition, c. third means, operative when said circuit is in said set condition, for causing said circuit to assume a stable state L1 or L0 corresponding to said input signal, and d. fourth means responsive to said circuit assuming a stable state L1 or L0 for switching said circuit out of said set condition.

Claim 6

A circuit having three stable states, L1, L0 and L and adapted to assume the stable state indicated by an input signal, said circuit comprising: a. first means responsive to a first externally applied input signal when said circuit is in a quiescent condition for causing said circuit to assume said stable state L , b. second means responsive to said circuit assuming said stable state L for switching said circuit to the set condition, c. third means, operative when said circuit is in said set condition, for causing said circuit to assume a stable state L1 or L0 corresponding to said input signal, and d. fourth means responsive to said circuit assuming a stable state L1 or L0 for switching said circuit out of said set condition.

Claim 7

A circuit as claimed in claim 3 wherein said first and third means in combination comprises: a. a gating circuit means responsive to input signals representing L1 and L0 and to an enabling signal for providing output signals corresponding to said input signals when said enabling signal is present and for providing an output signal corresponding to L when said enabling signal is not present, and b. a three state logic circuit having inputs connected to the output of said gating circuit means and a further input connected to receive said externally applied signal, said three state logic circuit being responsive to an input signal corresponding to L and to said externally applied signal for assuming a stable state corresponding to L ; said three state logic circuit being responsive to the absence of said externally applied signal and to the presence of an input signal corresponding to L1 or L0 for assuming a stable state L1 or L0, respectively.

Claim 8

A circuit as claimed in claim 3 wherein said second and fourth means, in combination, comprises: a control logic circuit having at least quiescent and set states and adapted to be switched sequentially between its states, and means responsive to the set state of said control logic circuit for connecting an enable signal to said third circuit means.

Claim 9

An asynchronous multi-stable state circuit comprising: a. a gating circuit means responsive to input signals representing first and second stable states and an enabling signal for providing at an output thereof gated output signals corresponding to said input signals when said enabling signal is present, and a third signal when said enabling signal is absent, b. a three state memory means having first, second and third stable states and said gated output signals and a clear signal supplied as inputs thereto, said memory being responsive to said clear signal and said gated output representing said third signal for causing said memory means to assume said third stable state, said memory means being responsive to the absence of said clear signal and the presence of a gated output representing said first or second stable states for causing said memory means to assume said first or second stable states, respectively, and c. a control circuit means connected to the output of said memory means and having a further input applied thereto, and having three states, quiescent, set and clear; said control circuit means being responsive to said memory means being in said third stable state for switching from said quiescent state to said set state and thereby providing an enabling signal to said gating circuit; said control circuit means being responsive to said memory means being in either said first or second stable states for causing said control circuit to switch from said set state to said clear state; and said control circuit means being responsive to said further input for causing said control circuit to switch from said clear state to said quiescent state.

Claim 10

An asynchronous multi-stable state circuit comprising: a. a gating circuit means responsive to input signals representing first and second stable states and an enabling signal for providing at an output thereof gated output signals corresponding to said input signals when said enabling signal is present, and a third signal when said enabling signal is absent, b. a three state memory means having first, second and third stable states and said gated output signals and a clear signal supplied as inputs thereto, said memory being responsive to said clear signal and said gated output representing said third signal for causing said memory means to assume said third stable state, said memory means being responsive to the absence of said clear signal and the presence of a gated output representing said first or second stable states for causing said memory means to assume said first or second stable states, respectively, and c. a control circuit means connected to the output of said memory means and having a further input applied thereto, and having three states, quiescent, set and clear; said control circuit means being responsive to said memory means being in said third stable state for switching from said quiescent state to said set state and thereby providing an enabling signal to said gating circuit; said control circuit means being responsive to said memory means being in either said first or second stable states for causing said control circuit to switch from said set state to said clear state; and said control circuit means being responsive to said further input for causing said control circuit to switch from said clear state to said quiescent state.

Claim 11

A shift register circuit means comprising a plurality of like stages, each said like stages adapted to store only one of three data items L1, L0 and L and having quiescent, set, and clear control states of operation, each said like stage comprising: a. means responsive to a clear signal from a succeeding stage of said shift register for storing the data L in said state, provided said stage is in the quiescent state, b. means responsive to the storage of data L in said stage for switching the control state of said stage from quiescent to set, c. means responsive to the data stored in a preceding stage of said shift register, provided said data is L1 or L0, for entering said data from said preceding stage into said stage for storage therein when said stage is in the set condition, d. means responsive to the storage of data L1 or L0 in said stage for switching said control state from set to clear control state, e. a means responsive to said control state of said stage for applying a clear signal to said preceding stage, and f. means responsive to said preceding stage storing the data L for switching the control state of said stage from clear to quiescent.

Claim 12

A shift register circuit means comprising a plurality of like stages, each said like stages adapted to store only one of three data items L1, L0 and L and having quiescent, set, and clear control states of operation, each said like stage comprising: a. means responsive to a clear signal from a succeeding stage of said shift register for storing the data L in said state, provided said stage is in the quiescent state, b. means responsive to the storage of data L in said stage for switching the control state of said stage from quiescent to set, c. means responsive to the data stored in a preceding stage of said shift register, provided said data is L1 or L0, for entering said data from said preceding stage into said stage for storage therein when said stage is in the set condition, d. means responsive to the storage of data L1 or L0 in said stage for switching said control state from set to clear control state, e. a means responsive to said control state of said stage for applying a clear signal to said preceding stage, and f. means responsive to said preceding stage storing the data L for switching the control state of said stage from clear to quiescent.