Patent US5030855A successfully refreshed from Google Patents.
US5030855A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current logic transceiver
Assignee: Renesas Electronics America Inc
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Filing: 1990-05-08
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Granted: 1991-07-09
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Expires: 2010-05-08
Abstract
Abstract For cummunication across a capacitively loaded line (108) a line driver (104) and a receiver (106) are used. The line driver (104) includes at least one gate (switch) (122) and at least one current mirror (120), the combination for selectively developing a current of predetermined level at the receiver output (108). The receiver (106) includes a current source (transistor) (202) for developing a current of predetermined level at an output (220). In addition, the receiver (106) also includes another current mirror (200) for converting the current level on the line (108) to a voltage level at the output (220).
Inventors
- 👤 Wingyu Leung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018557; H03K19/018571; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
120 words
A transceiver comprising in combination: a capacitively loaded line (108); a line driver (104) employing first switching means (122) and first current mirror means (120) connected to said line (108) and connected to said line driver (104) first switching means (122), said line driver (104) first current mirror means (120) for selectively developing on said line (108) a current of predetermined level; and a receiver (106) employing current source means (202) and first current mirror means (200) connected to said line (108) and connected to said receiver (106) current source means (202), said receiver (106) first current mirror means (200) for developing a voltage the level of which represents the level of the current selectively developed on said line (108).
Claim 2
Dependent Claim
120 words
A transceiver comprising in combination: a capacitively loaded line (108); a line driver (104) employing first switching means (122) and first current mirror means (120) connected to said line (108) and connected to said line driver (104) first switching means (122), said line driver (104) first current mirror means (120) for selectively developing on said line (108) a current of predetermined level; and a receiver (106) employing current source means (202) and first current mirror means (200) connected to said line (108) and connected to said receiver (106) current source means (202), said receiver (106) first current mirror means (200) for developing a voltage the level of which represents the level of the current selectively developed on said line (108).
Claim 3
Dependent Claim
84 words
A transceiver as recited in claim 1 wherein said line driver (104) first current mirror means (120) includes, a first transistor (130) having a gate connected to said line driver (104) first switching means (122) and a channel connected between a power supply potential and said line driver (104) first switching means (122), and a second transistor (132) having a gate connected to said line driver (104) first switching means (122) and a channel connected between the power supply potential and said line (108).
Claim 4
Dependent Claim
69 words
A transceiver as recited in claim 2 wherein said line driver (104) first switching means (122) includes, a first transistor (150) having a gate and a channel, and a second transistor (152) having a gate and a channel connected in series with said line driver (104) first switching means (122) first transistor (150) channel between said line driver (104) first current mirror means (120) and a circuit ground potential.
Claim 5
Dependent Claim
61 words
A transceiver as recited in claim 1 wherein said line driver (104) further employs second switching means (128) and second current mirror means (126) connected to said line (108) and connected to said line driver (104) second switching means (128), said line driver (104) second current mirror means (126) for selectively developing on said line (108) another current of predetermined level.
Claim 6
Dependent Claim
72 words
A transceiver as recited in claim 1 wherein said receiver (106) first current mirror means (200) includes, a first transistor (210) having a gate connected to said line (108) and a channel connected between said line (108) and a circuit ground potential, and a second transistor (212) having a gate connected to said line (108) and a channel connected between said receiver (106) current source means (202) and the circuit ground potential.
Claim 7
Dependent Claim
44 words
A transceiver as recited in claim 1 wherein said receiver (106) current source means (202) has a transistor (202) having a gate and a channel connected between a power supply potential and said receiver (106) first current mirror means (200) second transistor (212) channel.
Claim 8
Dependent Claim
49 words
A transceiver as recited in claim 1 wherein said receiver (106) current source means (202) has current sink means (254) and second receiver (106) current mirror means (202 and 250) connected to said receiver (106) first current mirror means (200) and to said receiver (106) current sink means (254).
Claim 9
Dependent Claim
71 words
A transceiver as recited in claim 7 wherein said receiver (106) first current mirror means (200) includes, a first transistor (210) having a gate connected to said line (108) and a channel connected between said line (108) and a circuit ground potential, and a second transistor (212) having a gate connected to said line (108) and a channel connected between receiver (106) current source means (202) and the circuit ground potential.
Claim 10
Dependent Claim
84 words
A transceiver as recited in claim 8 wherein said line driver (104) first current mirror means (120) includes, a first transistor (130) having a gate connected to said line driver (104) first switching means (122) and a channel connected between a power supply potential and said line driver (104) first switching means (122), and a second transistor (132) having a gate connected to said line driver (104) first switching means (122) and a channel connected between the power supply potential and said line (108).
Claim 11
Dependent Claim
469 words
A random-access-memory address decoder comprising in combination: a capacitively loaded line (108); a line driver (104) employing, first switching means (122) including, a first transistor (150) having a gate and a channel including a first and a second end, and a second transistor (152) having a gate and a channel connected between said line driver (104) first switching means (122) first transistor (150) channel first end and a circuit ground potential, first current mirror means (120) for selectively developing on said line (108) a current of predetermined level, said line driver (104) first current mirror means (120) including, a first transistor (130) having a gate connected to said line driver (104) first switching means (122) first transistor (150) channel second end and a channel connected between a power supply potential and said line driver (104) first switching means (122) first transistor (150) channel second end, and a second transistor (132) having a gate connected to said line driver (104) first switching means (122) first transistor (150) channel second end and a channel connected between the power supply potential and said line (108), second switching means (128) including, a first transistor (170) having a gate and a channel including a first and a second end, and a second transistor (172) having a gate and a channel connected between said line driver (104) second switching means (128) first transistor (170) channel first end and the circuit ground potential, second current mirror means (126) for selectively developing on said line (108) a current of predetermined level, said line driver (104) second current mirror means (126) including, a first transistor (160) having a gate connected to said line driver (104) second switching means (128) first transistor (170) channel second end and a channel connected between the power supply potential and said line driver (104) second switching means (128) first transistor (170) channel second end, and a second transistor (162) having a gate connected to said line driver (104) second switching means (128) first transistor (170) channel second end and a channel connected between the power supply potential and said line (108); and a receiver (106) employing current source means (202) and first current mirror means (200) connected to said line (108) and connected to said receiver (106) current source means (202), said receiver (106) first current mirror means (200) for developing a voltage the level of which represents the level of the current selectively developed on said line (108), said receiver (106) first current mirror means (200) including, a first transistor (210) having a gate connected to said line (108) and a channel connected between said line (108) and the circuit ground potential, and a second transistor (212) having a gate connected to said line (108) and a channel connected between said receiver (106) current source means (202) and the circuit ground potential.
Claim 12
Dependent Claim
469 words
A random-access-memory address decoder comprising in combination: a capacitively loaded line (108); a line driver (104) employing, first switching means (122) including, a first transistor (150) having a gate and a channel including a first and a second end, and a second transistor (152) having a gate and a channel connected between said line driver (104) first switching means (122) first transistor (150) channel first end and a circuit ground potential, first current mirror means (120) for selectively developing on said line (108) a current of predetermined level, said line driver (104) first current mirror means (120) including, a first transistor (130) having a gate connected to said line driver (104) first switching means (122) first transistor (150) channel second end and a channel connected between a power supply potential and said line driver (104) first switching means (122) first transistor (150) channel second end, and a second transistor (132) having a gate connected to said line driver (104) first switching means (122) first transistor (150) channel second end and a channel connected between the power supply potential and said line (108), second switching means (128) including, a first transistor (170) having a gate and a channel including a first and a second end, and a second transistor (172) having a gate and a channel connected between said line driver (104) second switching means (128) first transistor (170) channel first end and the circuit ground potential, second current mirror means (126) for selectively developing on said line (108) a current of predetermined level, said line driver (104) second current mirror means (126) including, a first transistor (160) having a gate connected to said line driver (104) second switching means (128) first transistor (170) channel second end and a channel connected between the power supply potential and said line driver (104) second switching means (128) first transistor (170) channel second end, and a second transistor (162) having a gate connected to said line driver (104) second switching means (128) first transistor (170) channel second end and a channel connected between the power supply potential and said line (108); and a receiver (106) employing current source means (202) and first current mirror means (200) connected to said line (108) and connected to said receiver (106) current source means (202), said receiver (106) first current mirror means (200) for developing a voltage the level of which represents the level of the current selectively developed on said line (108), said receiver (106) first current mirror means (200) including, a first transistor (210) having a gate connected to said line (108) and a channel connected between said line (108) and the circuit ground potential, and a second transistor (212) having a gate connected to said line (108) and a channel connected between said receiver (106) current source means (202) and the circuit ground potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-08 | 1995-01-07 | 1995-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-08 | 1999-01-07 | 1999-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-08 | 2003-01-07 | 2003-07-09 | $7700.00 | Window Closed / Lapsed |