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US5030581A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabricating a semiconductor apparatus

Assignee: Toshiba Corp
•
Filing: 1989-11-13
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Granted: 1991-07-09
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Expires: 2009-11-13
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Abstract

Abstract A semiconductor apparatus comprises a semiconductor body of one conductivity type; a first impurity region of an opposite conductivity type, which is formed in the surface area of the semiconductor body; impurity regions of the opposite conductivity type, formed in the surface area of the semiconductor body, at locations away from the first impruity region; second and third impurity regions of one conductivity type, which seve as source and drain regions, respectively, and are formed in the impurity regions of an opposite conductivity type, so as to sandwich a channel reigon; and a gate electrode formed on the channel region, through an insulative layer. In this semiconductor apparatus, the impurity regions of the opposite conductivity type include fourth and fifth impurity regions, formed in the channel region such that at least parts of the fourth and fifth impurity regions overlap.

Inventors

  • 👤 Shigenori Yakushiji
  • 👤 Kouji Jitsukata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 15:30
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D8/00; H10D8/80; H10D84/00; H10D84/101; H10D84/131; H10D84/138; H10D84/40; H10D84/401

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 184 words
A method of manufacturing a semiconductor apparatus, comprising the steps of: forming an insulative layer on a semiconductor body of one conductivity type; forming first and second opening portions on said insulative layer, such that said portions are located away from each other; forming an insulative film thinner than said insulative layer on said semiconductor base material exposed in said first and second opening portions; forming a gate electrode on the insulative film in said second opening portion; forming a first impurity region in the portion corresponding to said first opening portion, by implanting impurities of an opposite conductivity type in said semiconductor base material, through said first and second opening portions, by using said insulative layer and said gate electrode as masks, and forming second and third impurity regions in the portion corresponding to said second opening portion, so that parts of said second and third impurity regions overlap; and forming fourth and fifth impurity regions, serving as a source and a drain, respectively, by implanting impurities of one conductivity type into said second and third impurity regions, through the second opening portion.
Claim 2
Independent Claim 184 words
A method of manufacturing a semiconductor apparatus, comprising the steps of: forming an insulative layer on a semiconductor body of one conductivity type; forming first and second opening portions on said insulative layer, such that said portions are located away from each other; forming an insulative film thinner than said insulative layer on said semiconductor base material exposed in said first and second opening portions; forming a gate electrode on the insulative film in said second opening portion; forming a first impurity region in the portion corresponding to said first opening portion, by implanting impurities of an opposite conductivity type in said semiconductor base material, through said first and second opening portions, by using said insulative layer and said gate electrode as masks, and forming second and third impurity regions in the portion corresponding to said second opening portion, so that parts of said second and third impurity regions overlap; and forming fourth and fifth impurity regions, serving as a source and a drain, respectively, by implanting impurities of one conductivity type into said second and third impurity regions, through the second opening portion.

References Cited (Backward Citations)

US4084311A Cited
US4205342A Cited
US4306916A Cited
US4287661A Cited
US4783424A Cited
JPS61180484A Cited
US4713329A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-07-08 1995-01-07 1995-07-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-07-08 1999-01-07 1999-07-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-07-08 2003-01-07 2003-07-09 $7700.00 Window Closed / Lapsed

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