Single transistor non-valatile electrically alterable semiconductor memory device

Claim 2

An electrically programmable and erasable memory device having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a common line, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor, said single transistor comprising: a source coupled to said common line; a drain coupled to an associated one of the plurality of column address lines; a control gate coupled to an associated one of the plurality of row address lines; a floating gate positioned between the control gate and the source and the drain and being capacitively coupled to the drain; means for injecting hot electrons generated by abrupt potential drop onto the floating gate when the associated ones of the column address and row address lines are raised to a first predetermined potential above that of the common line, with the potential applied to said associated one of the column address lines being above the potential applied to said associated one of the row address lines; and means for inducing Fowler-Nordheim tunneling of charges from the floating gate to the control gate when the associate row address line is raised to a second predetermined potential above the associated column address line.

Claim 3

The device of claim 1, wherein the injecting and inducing means comprises: a first layer of insulating material, having a dielectric constant and a thickness, positioned between the floating gate and the drain for providing a high capacitance between the floating gate and the drain; and a second layer of insulating material, having a dielectric constant and a thickness, positioned between the floating gate and the control gate for providing a minimal capacitance between the floating gate and the control gate and for permitting Fowler-Nordheim tunneling therebetween.

Claim 4

An electrically programmable and erasable memory device comprising: a substrate of semiconductor material of a first conductivity type; first and second spaced-apart regions in said substrate of a second conductivity type, with a channel region therebetween; a first insulating layer disposed over said substrate including over said first, second and channel regions; an electrically conductive floating gate disposed over said first insulating layer and extending over a portion of said channel region and over a portion of said second region to maximize a capacitive coupling therewith; a second insulating layer disposed over and adjacent said floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and an electrically conductive control gate having two electrically connected sections, a first section disposed over said first insulating layer, spaced apart from said floating gate and adjacent to said second insulating layer, extending over a portion of said first region; said second section disposed over said second insulating layer to minimize capacitive coupling with said floating gate.

Claim 5

An electrically programmable and erasable memory device comprising: a substrate of semiconductor material of a first conductivity type; first and second spaced-apart regions in said substrate of a second conductivity type, with a channel region therebetween; a first insulating layer disposed over said substrate including over said first, second and channel regions; an electrically conductive floating gate disposed over said first insulating layer and extending over a portion of said channel region and over a portion of said second region to maximize a capacitive coupling therewith; a second insulating layer disposed over and adjacent said floating gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough; and an electrically conductive control gate having two electrically connected sections, a first section disposed over said first insulating layer, spaced apart from said floating gate and adjacent to said second insulating layer, extending over a portion of said first region; said second section disposed over said second insulating layer to minimize capacitive coupling with said floating gate.

Claim 6

The device of claim 3, wherein said first insulating layer is silicon dioxide, silicon nitride or silicon oxynitride and is on the order of 70-200 angstroms in thickness.

Claim 7

The device of claim 3, wherein said second insulating layer, adjacent to said floating gate, is silicon dioxide, silicon nitride or silicon oxynitride and is on the order of 150-1200 angstroms in thickness.

Claim 8

In a method of operating an electrically programmable and erasable memory device of the type having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a common line, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor having a source coupled to said common line, a drain coupled to an associated one of the plurality of column address lines, a control gate coupled to an associated one of the plurality of row address lines, and a floating gate for the storage of charges thereon, said floating gate being capacitively coupled to said drain and to said control gate, wherein said method comprising the steps of: erasing a first plurality of said storage sites by: applying a ground potential to said common line; applying a ground potential to a first plurality of column address lines associated with the first plurality of said storage sites; applying a first positive potential to a first plurality of row address lines associated with the first plurality of said storage sites thereby causing charges on said floating gate at each of said storage sites to be transferred to the control gate at each of said storage sites through Fowler-Nordheim tunneling; selectively programming a second plurality of said storage sites from the first plurality of storage sites erased by: applying a ground potential to said common line; applying a second positive potential to a second plurality of column address lines associated with the second plurality of said storage sites; and applying a third positive potential, less than said second positive potential, to a second plurality of row address lines associated with the second plurality of said storage sites, thereby causing electrons from the source of each storage site to be transferred to the floating gate by hot electron generated by abrupt potential drop.

Claim 9

In a method of operating an electrically programmable and erasable memory device of the type having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a common line, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor having a source coupled to said common line, a drain coupled to an associated one of the plurality of column address lines, a control gate coupled to an associated one of the plurality of row address lines, and a floating gate for the storage of charges thereon, said floating gate being capacitively coupled to said drain and to said control gate, wherein said method comprising the steps of: erasing a first plurality of said storage sites by: applying a ground potential to said common line; applying a ground potential to a first plurality of column address lines associated with the first plurality of said storage sites; applying a first positive potential to a first plurality of row address lines associated with the first plurality of said storage sites thereby causing charges on said floating gate at each of said storage sites to be transferred to the control gate at each of said storage sites through Fowler-Nordheim tunneling; selectively programming a second plurality of said storage sites from the first plurality of storage sites erased by: applying a ground potential to said common line; applying a second positive potential to a second plurality of column address lines associated with the second plurality of said storage sites; and applying a third positive potential, less than said second positive potential, to a second plurality of row address lines associated with the second plurality of said storage sites, thereby causing electrons from the source of each storage site to be transferred to the floating gate by hot electron generated by abrupt potential drop.