Bipolar SRAM having word lines as vertically stacked pairs of conductive lines parallelly formed with holding current lines

Claim 2

A semiconductor memory device comprising: a semiconductor body having a main surface; a plurality of memory cells formed on said main surface, each memory cell having a pair of bipolar transistors; a memory cell array including a word line and a plurality of pairs of complementary digit lines, said word and complementary digit lines being coupled to selection circuits and being coupled to said memory cells so that each memory cell is coupled to said word line and to a pair of complementary digit lines, said word line including first and second lines each made of a separate conductive layer material extended over a region where said memory cells are formed; and a current line coupled to a current source circuit on said main surface and being coupled to each memory cell, said current line being made of a conductive layer material extended along a direction corresponding to that of said word line and over said region where said memory cells are formed, wherein said second line is stacked over said first line, and wherein said first and second lines are electrically connected to each other at predetermined intervals along the lengths of said first and second lines through respective openings formed in an insulating film which is interposed between the separate conductive layer materials which form said first and second lines.

Claim 3

A semiconductor memory device according to claim 1, wherein the second line of said word line has a width which is greater than that of said first line.

Claim 4

A semiconductor memory device according to claim 2, wherein the first line of said word line and said current line are made of the same conductive layer material, and wherein the second line of said word line extends over said current line so that the second line of said word line is stacked over said current line.

Claim 5

A semiconductor memory device according to claim 3, wherein said insulating film interposed between the separate conductive layer materials which form said first and second lines further extends over said current line, and wherein said second line and said current line are electrically isolated from each other by said insulating film extended over said current line.

Claim 6

A semiconductor memory device according to claim 1, wherein said pair of bipolar transistors of each memory cell are composed of first and second bipolar transistors, wherein a collector of said first bipolar transistor is coupled to a base of said second bipolar transistor and a collector of said second bipolar transistor is coupled to a base of said first bipolar transistor, and wherein each of said first and second bipolar transistors has at least a first emitter, said first emitters thereof are coupled to a corresponding one of a pair of complementary digit lines.

Claim 7

A semiconductor memory device according to claim 5, wherein each one of said first and second bipolar transistors further comprises a second emitter, and wherein said second emitters of said first and second bipolar transistors are coupled to each other and to said current line coupled to said current source circuit.

Claim 8

A semiconductor memory device according to claim 6, wherein each of said memory cells further comprises a first load circuit coupling the collector of said first bipolar transistor to said word line and a second load circuit coupling the collector of said second bipolar transistor to said word line.

Claim 9

A semiconductor memory device according to claim 7, wherein said first and second load circuits of each of said memory cells comprise first and second parallel connections, respectively, each one thereof including a parallel arrangement of a resistance element, a Schottky barrier diode and a capacitor.

Claim 10

A semiconductor memory device comprising: a semiconductor body having a main surface; a plurality of memory cells formed on said main surface, each memory cell having a pair of bipolar transistors; a memory cell array including a plurality of word lines and a plurality of pairs of complementary digit lines, said word and complementary digit lines being coupled to selection circuits and being coupled to said memory cells so that each memory cell is correspondingly coupled to a word line and to a pair of complementary digit lines, each of said word lines being extended in a predetermined direction and each pair of complementary digit lines being extended in a substantially orthogonal direction to said predetermined direction above said main surface, wherein each one of said word lines includes a first wiring layer and a second wiring layer stacked over said first wiring layer, and wherein each word line extends over a region where said memory cells which are correspondingly coupled therewith are formed; a plurality of current lines, each one thereof being coupled to a current source circuit on said main surface and being coupled to memory cells correspondingly with a respective word line, wherein each one of said current lines includes a third wiring layer which extends along a direction common to the direction of the corresponding word line and over said region where memory cells correspondingly coupled therewith are formed; and an insulating film interposed between said first and second wiring layers of each one of said plurality of word lines, wherein said first and second wiring layers of each one of said plurality of word lines are electrically connected to each other at predetermined intervals along said predetermined direction through respective openings formed in said insulating film.

Claim 11

A semiconductor memory device comprising: a semiconductor body having a main surface; a plurality of memory cells formed on said main surface, each memory cell having a pair of bipolar transistors; a memory cell array including a plurality of word lines and a plurality of pairs of complementary digit lines, said word and complementary digit lines being coupled to selection circuits and being coupled to said memory cells so that each memory cell is correspondingly coupled to a word line and to a pair of complementary digit lines, each of said word lines being extended in a predetermined direction and each pair of complementary digit lines being extended in a substantially orthogonal direction to said predetermined direction above said main surface, wherein each one of said word lines includes a first wiring layer and a second wiring layer stacked over said first wiring layer, and wherein each word line extends over a region where said memory cells which are correspondingly coupled therewith are formed; a plurality of current lines, each one thereof being coupled to a current source circuit on said main surface and being coupled to memory cells correspondingly with a respective word line, wherein each one of said current lines includes a third wiring layer which extends along a direction common to the direction of the corresponding word line and over said region where memory cells correspondingly coupled therewith are formed; and an insulating film interposed between said first and second wiring layers of each one of said plurality of word lines, wherein said first and second wiring layers of each one of said plurality of word lines are electrically connected to each other at predetermined intervals along said predetermined direction through respective openings formed in said insulating film.

Claim 12

A semiconductor memory device according to claim 9, wherein the second line of each one of said word lines has a width which is greater than that of said first line.

Claim 13

A semiconductor memory device according to claim 10, wherein the first line of each one of said plurality of word lines and said plurality of current lines are made of the same conductive layer material, and wherein the second line of each one of said plurality of word lines respectively extends over a corresponding one of said plurality of current lines so that the second line of each one of said plurality of word lines is stacked over a corresponding one of said plurality of current lines.

Claim 14

A semiconductor memory device according to claim 11, wherein with respect to each word line and corresponding current line said insulating film interposed between the separate conductive layer materials which form said first and second lines further extends over said current line, and wherein the second line of each one of said plurality of word lines and each corresponding one of said plurality of current lines are electrically isolated from each other by said insulating film extended over said current line.

Claim 15

A semiconductor memory device according to claim 9, wherein said pair of said bipolar transistors of each memory cell are composed of first and second bipolar transistors, wherein a collector of said first bipolar transistor is coupled to a base of said second bipolar transistor and a collector of said second bipolar transistor is coupled to a base of said first bipolar transistor, and wherein each of said first and second bipolar transistors has at least a first emitter, said first emitters thereof are coupled to a corresponding one of a pair of complementary digit lines.

Claim 16

A semiconductor memory device according to claim 13, wherein each one of said first and second bipolar transistors further comprises a second emitter, and wherein said second emitters of said first and second bipolar transistors are coupled to each other and to one of said plurality of current lines coupled to said current source circuit.

Claim 17

A semiconductor memory device according to claim 14, wherein each of said memory cells further comprises a first load circuit coupling the collector of said first bipolar transistor to a corresponding one of said plurality of word lines and a second load circuit coupling the collector of said second bipolar transistor to said corresponding word line.

Claim 18

A semiconductor memory device according to claim 15, wherein said first and second load circuits of each of said memory cells comprise first and second parallel connections, respectively, each one thereof including a parallel arrangement of a resistance element, a Schottky barrier diode and a capacitor.