Circuit arrangement for processing analogue electrical signals

Claim 2

A circuit arrangement for processing sampled analogue electrical signals, each sample being in the form of a current, the circuit arrangement comprising: means for combining in predetermined proportions an input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving a processed output signal as or from the combined current produced by the combining means in successive sample periods, and for scaling a current, which scaling means comprises a first branch for receiving a current to be scaled, second and third branches for producing first and second sub-output currents which are proportional to the received current, means for forming a difference current between the first and second sub-output currents, and means for feeding the difference current to the output of the current scaling means.

Claim 3

A current mirror circuit arrangement for scaling a current comprising: an input branch including a first diode connected field effect transistor, a first sub-output branch including a second field effect transistor, and a second sub-output branch including a third field effect transistor, means for forming a current which is the difference between currents in the first and second sub-output branches, and means for feeding the difference current to an output of the current mirror circuit.

Claim 4

A current mirror circuit arrangement for scaling a current comprising: an input branch including a first diode connected field effect transistor, a first sub-output branch including a second field effect transistor, and a second sub-output branch including a third field effect transistor, means for forming a current which is the difference between currents in the first and second sub-output branches, and means for feeding the difference current to an output of the current mirror circuit.

Claim 5

A current mirror circuit arrangement as claimed in claim 2 wherein the means for forming the difference current comprises means for inverting the current produced in one of the sub-output branches, and means for applying to a summing junction the inverted current and a current from the other sub-output branch.

Claim 6

A current mirror circuit arrangement as claimed in claim 3 wherein the inverting circuit comprises a further current mirror circuit including transistors of the opposite conductivity type from the first, second and third transistors, and wherein an output of said one of the sub-output branches is fed to an input of the further current mirror circuit and an output of the further current mirror circuit is coupled to the summing junction.

Claim 7

A circuit arrangement as claimed in claim 1 wherein the means for scaling a current comprise a current conveyor circuit, said current conveyor circuit comprising an x-input connected to an input branch for receiving the current to be scaled, a y-input connected to a reference potential, first and second sub-output branches for producing said first and second sub-output currents which are proportional to the received current, said current conveyor circuit also including said means for forming the difference between the first and second sub-output currents and wherein said feeding means feeds the difference current to the z-output of the current conveyor circuit.

Claim 8

A current mirror arrangement as claimed in claim 2 wherein the current scaling means comprises means for regularly isolating the input branch from the sub-output branches and means for maintaining current flow in the sub-output branches when they are isolated from the input branch.

Claim 9

A current mirror circuit arrangement as claimed in claim 6 wherein the isolating means comprises a switch controlled by a clock signal and the maintaining means comprises a capacitor.

Claim 10

A current mirror circuit arrangement as claimed in claim 7 in which the capacitor is connected between the source and gate electrodes of the second field effect transistor.

Claim 11

A circuit arrangement as claimed in claim 1 wherein the current scaling means produce a scaled bi-directional input current, the current scaling means comprising: means for adding a bias current to the bi-directional input current to produce a uni-directional current, wherein said scaling means scales the uni-directional current, and means for subtracting a suitably scaled bias current from a scaled unit-directional current to produce an output bi-directional current.

Claim 12

A circuit arrangement as claimed in claim 9, wherein said current scaling means are arranged to scale a differential input current to produce a scaled differential output current.

Claim 13

A circuit arrangement as claimed in claim 1 further comprising a current mirror circuit as claimed in claim 6.

Claim 14

A circuit arrangement as claimed in claim 11 wherein the current mirror circuit comprises a current memory circuit arranged to store a bi-directional input current comprising means for adding a bias current to the bi-directional input current to produce a uni-directional current, means for storing the uni-directional current, and means for subtracting a bias current from the stored uni-directional current to produce a bi-directional output current.

Claim 15

A circuit arrangement as claimed in claim 11 wherein the current mirror circuit is arranged to store a differential input current.

Claim 16

A circuit arrangement as claimed in claim 1 wherein the current scaling means comprises means for regularly isolating the first branch from the second and third branches and means for maintaining current flow in the second and third branches when they are isolated from the first branch.

Claim 17

A current mirror circuit arrangement as claimed in claim 2 wherein the current scaling means produce a scaled bi-directional output current from a bi-directional input current, the current scaling means comprising: means for adding a bias current to the bi-directional input current to produce a uni-directional current, wherein said scaling means scales the uni-directional current, and means for subtracting a suitably scaled bias current from a scaled uni-directional current to produce an output bi-directional current.

Claim 18

A circuit for processing sampled analog electric current signals comprising: an input for receiving sampled analog current signals, means for combining an input sample current in a sample period with a current derived form an input sample current received in at least one preceding sample period, a current memory circuit and a first current scaling circuit connected in cascade between said input and a first input of said combining means, a second current scaling circuit connected between said input and a second input of the combining means, and an output terminal coupled to an output of said combining means, wherein at least one of said current scaling circuits comprises; a first branch circuit for receiving a current to be scaled, second and third sub-output branch circuits for supplying first and second sub-output currents proportional to the current in the first branch circuit, and means responsive to said first and second sub-output currents for deriving a difference current thereof at an output of said current scaling circuit.

Claim 19

A circuit for processing sampled analog electric current signals comprising: an input for receiving sampled analog current signals, means for combining an input sample current in a sample period with a current derived form an input sample current received in at least one preceding sample period, a current memory circuit and a first current scaling circuit connected in cascade between said input and a first input of said combining means, a second current scaling circuit connected between said input and a second input of the combining means, and an output terminal coupled to an output of said combining means, wherein at least one of said current scaling circuits comprises; a first branch circuit for receiving a current to be scaled, second and third sub-output branch circuits for supplying first and second sub-output currents proportional to the current in the first branch circuit, and means responsive to said first and second sub-output currents for deriving a difference current thereof at an output of said current scaling circuit.

Claim 20

A processing circuit as claimed in claim 16 wherein said difference current deriving means comprises means for inverting the current produced in one of the sub-output branch circuits, and means for applying to a summing junction the inverted current and a current from the other sub-output branch circuit.

Claim 21

A processing circuit as claimed in claim 15 wherein said first, second and third branch circuits together form a first current mirror circuit comprising a first diode connected field effect transistor in the first branch circuit and second and third field effect transistors in the second and third branch circuits, respectively, said difference current deriving means receiving said first and second sub-output currents thereby to supply the difference current to an output of the first current mirror circuit.

Claim 22

A processing circuit as claimed in claim 16 wherein said first, second and third branch circuits together form a first current mirror circuit comprising a first diode-connected field effect transistor in the first branch circuit and second and third field effect transistors in the second and third branch circuits, respectively, said difference current deriving means comprising means for inverting the current produced in one of the sub-output branch circuits, and means for applying to a summing junction the inverted current and a current from the other sub-output branch circuit, wherein said first, second and third field effect transistors are of the same conductivity type, and wherein the inverting circuit comprises a further current mirror circuit including transistors of the opposite conductivity type to that of the first, second and third field effect transistors, and wherein an output of said one of the sub-output branch circuits is fed to an input of the further current mirror circuit and an output of the further current mirror circuit is coupled to the summing junction.

Claim 23

A processing circuit as claimed in claim 16 wherein said current memory circuit comprises first and second current mirror circuits each of which comprises: an input branch circuit and an output branch circuit, switching means for periodically isolating the input branch circuit from the output branch circuit, an energy storage element in the output branch circuit to maintain a current flow in the output branch circuit during those time periods when the input branch circuit is periodically isolated from the output branch circuit, and wherein the output branch circuit of the first current mirror circuit is coupled to the input branch circuit of the second current mirror circuit and the output branch circuit of the second current mirror circuit is coupled to an input of the first current scaling circuit.