US5027995A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for bonding semiconductor chips to substrates
Assignee: Siemens AG
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Filing: 1991-02-19
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Granted: 1991-07-02
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Expires: 2011-02-19
Abstract
Abstract A semiconductor chip (1) is bonded to a substrate (2) serving as a component housing, a contact part, an insulative part or a connecting part without the use of a high-temperature process or any additional bonding medium such as solder or flux. The backside of the semiconductor chip (1) or substrate (2) is structured to include specially formed bumps (3) for the necessary connections. A ductile metal is used for these bumps (3). The bond to the substrate (2) is formed by using pressure and/or ultrasonic energy. The process according to this invention is particularly suitable for bonding components in data link receivers, optoelectronic couplers, transmitters (LEDs, IREDs) and ISDN modules.
Inventors
- 👤 Alois Karl
- 👤 Karl Osojnik
- 👤 Werner Spaeth
- 👤 Guenther Waitl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:11
CPC Classifications
H; H10; H10H; H10H20/00; H10H20/80; H10H20/83; H10H20/832; H10F; H10F77/00; H10F77/50; H10W; H10W72/00; H10W72/20; H10W72/071; H10W72/072; H10W72/07231; H10W72/07232; H10W72/07233; H10W72/07236; H10W72/251; H10W72/252; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
113 words
A process for bonding a semiconductor chip to a substrate, comprising the steps of: forming a first bump of ductile metal having a first predetermined size on one of the semiconductor chip or substrate; forming a second bump of ductile metal on the first bump, the second bump having a second predetermined size smaller than the first predetermined size of the first bump; and bonding the semiconductor chip to the substrate by means of one or both of pressure and ultrasonic energy applied to the bumps; the first and second predetermined sizes being such that when bonding force is applied to the bumps, the geometry of the first bump is not affected significantly.
Claim 2
Dependent Claim
113 words
A process for bonding a semiconductor chip to a substrate, comprising the steps of: forming a first bump of ductile metal having a first predetermined size on one of the semiconductor chip or substrate; forming a second bump of ductile metal on the first bump, the second bump having a second predetermined size smaller than the first predetermined size of the first bump; and bonding the semiconductor chip to the substrate by means of one or both of pressure and ultrasonic energy applied to the bumps; the first and second predetermined sizes being such that when bonding force is applied to the bumps, the geometry of the first bump is not affected significantly.
Claim 3
Dependent Claim
18 words
A process according to claim 1, wherein the ductile metal used for bumps is aluminum, silver or gold.
Claim 4
Dependent Claim
28 words
A process according to claim 1, wherein the diameter of bumps is 10 μm to 50 μm and the height of bumps is 5 μm to 40 μm.
Claim 5
Dependent Claim
28 words
A process according to claim 2, wherein the diameter of bumps is 10 μm to 50 μm and the height of bumps is 5 μm to 40 μm.
Claim 6
Dependent Claim
20 words
A process according to claim 1, wherein the substrate is preheated to temperatures of about 180° C. to 300° C.
Claim 7
Dependent Claim
20 words
A process according to claim 2, wherein the substrate is preheated to temperatures of about 180° C. to 300° C.
Claim 8
Dependent Claim
20 words
A process according to claim 3, wherein the substrate is preheated to temperatures of about 180° C to 300° C.
Claim 9
Dependent Claim
20 words
A process according to claim 4, wherein the substrate is preheated to temperatures of about 180° C. to 300° C.
Claim 10
Dependent Claim
39 words
A process according to claim 1, for bonding semiconductor chips, integrated semiconductor circuits, light-emitting diodes to photodiodes or a conducting track, a photodiode to a pre-amplifier, a laser diode to a heat sink or chip capacitors, and chip resistors.
Claim 11
Dependent Claim
39 words
A process according to claim 2, for bonding semiconductor chips, integrated semiconductor circuits, light-emitting diodes to photodiodes or a conducting track, a photodiode to a pre-amplifier, a laser diode to a heat sink or chip capacitors, and chip resistors.
Claim 12
Dependent Claim
39 words
A process according to claim 3, for bonding semiconductor chips, integrated semiconductor circuits, light-emitting diodes to photodiodes or a conducting track, a photodiode to a pre-amplifier, a laser diode to a heat sink or chip capacitors, and chip resistors.
Claim 13
Dependent Claim
39 words
A process according to claim 5, for bonding semiconductor chips, integrated semiconductor circuits, light-emitting diodes to photodiodes or a conducting track, a photodiode to a pre-amplifier, a laser diode to a heat sink or chip capacitors, and chip resistors.
References Cited (Backward Citations)
US3838984A
Cited
JPS5419652A
Cited
DE3025859A1
Cited
DE3209242A1
Cited
US4607779A
Cited
US4754912A
Cited
US4784972A
Cited
DE3531235A1
Cited
JPS61287138A
Cited
US4693770A
Cited
US4887760A
Cited
US4857671A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |