Method and apparatus for dynamic data block length adjustment

Claim 1

A bus data block length selection apparatus for use with a data bus having a clock signal and a data-transfer-in-process signal, comprising: time base means connected for receiving said clock signal and for providing a pulse output after a preselected sample period; accumulator means responsive to said pulse output and said data-transfer-in-process signal for accumulating a total of said clock signals within each preselected sample period that jointly occur with said data-transfer-in-process signal and outputting a digital signal representative of said total; and decoder means responsive to said pulse output and to said digital signal output for decoding said digital signal output and selecting an appropriate length for a subsequent bus data block according to the total of said clock signals accumulated in said preselected sample period.

Claim 23

An apparatus for controlling a length of a data block on a data bus, comprising: a counter means connected to a bus clock for counting a first plurality of bus clock cycles and outputting a reference signal upon completion of said counting; a second counter means connected to said bus clock, said reference signal output and to a data-transfer-in-process signal output for counting a second plurality of bus clock cycles that occur concomitantly with said data-transfer-in-process signal, said second counter outputting a plurality of parallel signals corresponding to a plurality of most significant digits of said second plurality count; means for latching said plurality of parallel signals connected to said second counter output and said reference pulse, said latching means responsive to said reference pulse to enable said latch means to latch said parallel signals therein and hold said plurality of signals as outputs thereof; and decoder means responsive to said latch outputs for selecting a more appropriate data block length for a subsequent data block transmission on said data bus.

Claim 24

An apparatus for controlling a length of a data block on a data bus, comprising: a counter means connected to a bus clock for counting a first plurality of bus clock cycles and outputting a reference signal upon completion of said counting; a second counter means connected to said bus clock, said reference signal output and to a data-transfer-in-process signal output for counting a second plurality of bus clock cycles that occur concomitantly with said data-transfer-in-process signal, said second counter outputting a plurality of parallel signals corresponding to a plurality of most significant digits of said second plurality count; means for latching said plurality of parallel signals connected to said second counter output and said reference pulse, said latching means responsive to said reference pulse to enable said latch means to latch said parallel signals therein and hold said plurality of signals as outputs thereof; and decoder means responsive to said latch outputs for selecting a more appropriate data block length for a subsequent data block transmission on said data bus.

Claim 26

An apparatus for controlling a length of a data block on a data bus connecting multiple bus masters, comprising: a counter means connected to a bus clock for counting a first plurality of bus clock cycles and outputting a reference signal upon completion of said counting; a second counter means connected to said bus clock, said reference signal output, a local data-transfer-in-process signal output and an external data-transfer-in-process signal output for counting a second plurality of bus clock cycles that occur concomitantly with said external data-transfer-in-process signal, said second counter outputting a plurality of parallel signals corresponding to a plurality of most significant digits of said second plurality count; means for latching said plurality of parallel signals connected to said second counter output and said reference pulse, said latching means responsive to said reference pulse to enable said latch means to latch said parallel signals therein and hold said plurality of signals as outputs thereof; and decoder means responsive to said latch outputs for selecting a more appropriate data block length for a subsequent data block transmission on said data bus.

Claim 27

An apparatus for controlling a length of a data block on a data bus connecting multiple bus masters, comprising: a counter means connected to a bus clock for counting a first plurality of bus clock cycles and outputting a reference signal upon completion of said counting; a second counter means connected to said bus clock, said reference signal output, a local data-transfer-in-process signal output and an external data-transfer-in-process signal output for counting a second plurality of bus clock cycles that occur concomitantly with said external data-transfer-in-process signal, said second counter outputting a plurality of parallel signals corresponding to a plurality of most significant digits of said second plurality count; means for latching said plurality of parallel signals connected to said second counter output and said reference pulse, said latching means responsive to said reference pulse to enable said latch means to latch said parallel signals therein and hold said plurality of signals as outputs thereof; and decoder means responsive to said latch outputs for selecting a more appropriate data block length for a subsequent data block transmission on said data bus.

Claim 29

A method for controlling a length of a data block of a data bus, comprising: counting a preselected number of cycles of a reference clock of said data bus; generating a control pulse when said preselected number of cycles has been counted; counting a second number of cycles of said reference clock that occur concomitantly with a data-transmission-in-process signal of said data bus to measure a level of data block traffic during said preselected number of cycles; outputting a plurality of binary signals corresponding to a plurality of most significant bits of said second number; storing said plurality of binary signals in a storage means controlled by said control pulse; and decoding said binary signals stored in said storage means for selecting the length of a subsequently transmitted data block to efficiently optimally operated the data bus according to the level of bus traffic.

Claim 30

A method for controlling a length of a data block of a data bus, comprising: counting a preselected number of cycles of a reference clock of said data bus; generating a control pulse when said preselected number of cycles has been counted; counting a second number of cycles of said reference clock that occur concomitantly with a data-transmission-in-process signal of said data bus to measure a level of data block traffic during said preselected number of cycles; outputting a plurality of binary signals corresponding to a plurality of most significant bits of said second number; storing said plurality of binary signals in a storage means controlled by said control pulse; and decoding said binary signals stored in said storage means for selecting the length of a subsequently transmitted data block to efficiently optimally operated the data bus according to the level of bus traffic.