Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions

Claim 1

A split-polysilicon process for creating CMOS DRAM circuitry having self-alignedly silicided transistor gates and N+active areas, on a silicon substrate having both N-type material regions and P-type material regions, both types of said regions being covered by a gate dielectric layer, said process comprising the following sequential steps: a) blanket deposition of a first polysilicon layer on top of the gate dielectric layer; b) masking of said first polysilicon layer with a first photomask which, in P-type material regions, defines N-channel gates and interconnects and in N-type material regions, blankets said first polysilicon layer; c) removal of those portions of said first polysilicon layer that are not subjacent to the first photomask with a first polysilicon etch; d) stripping of said first photomask; e) self-aligned, implant of a P-type conductivity-creating impurity which functions as a punch-through implant in N-channel active areas; f) blanket deposition of a silicon dioxide spacer layer; g) anisotropically etching the silicon dioxide spacer layer to create N-channel transistor gate spacers and remove all silicon dioxide from N-channel active areas; h) self-aligned, high-dosage implanting of an N-type conductivity-creating impurity to create heavily-doped drain and source regions for N-channel transistors; i) blanket deposition of a first silicon nitride layer; j) blanket deposition of a second polysilicon layer; k) creation of a second photomask on top of previously deposited layers, said second photomask defining a cell plate; l) removal of those portions of said second polysilicon layer that are not subjacent to the second photomask with a second polysilicon etch to create the cell plate; m) stripping of the second photomask; n) using a third photomask to blanket the P-type material regions and to define the P-channel gates and interconnects in the N-type material regions; o) removal of those portions of said first nitride layer that are not subjacent to the third photomask with a nitride etch; p) removal of those portions of the first polysilicon layer that were exposed by the nitride etch with a third polysilicon etch; q) self-aligned, high-dosage implanting of a P-type conductivity-creating impurity to create heavily-doped drain and source regions for P-channel transistors; r) oxidation of all exposed silicon, whether of the polycrystalline or monocrystalline types; s) removal of all exposed silicon nitride with a nitride etch; t) deposition of a refractory metal layer; u) sintering of the refractory metal layer to create refractory metal silicide on unoxidized silicon surfaces; v) removal of all refractory metal that has not been converted to silicide.